Apparatus for transfer of data units between buses

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364DIG1, G06F 1206

Patent

active

052652289

ABSTRACT:
The present invention includes a data transfer system (28) which includes a first bus (32) and a second bus (34) wherein both buses are bidirectionally connected to a first memory (30). Similarly, a third bus (42) and a fourth bus (44) are bidirectionally connected to a second memory (40). A plurality of data cells (50a through 50h) are provided for intermediate storage when units of information are transferred between first and second memories (30 and 40). A first pointer (37) is under control of first pointer circuit (36) and first control circuit (38) such that buses (32 and 34) may have access to selected ones of the plurality of data cells (50a through 50h). Similarly, a second pointer (47) is under control of second pointer circuit (46) and second control circuit (48) such that third and fourth buses (42 and 44) may have access to the plurality of data cells (50a through 50h).

REFERENCES:
patent: 4489379 (1984-12-01), Lanier et al.
patent: 4642755 (1987-02-01), Hinch
patent: 4649479 (1987-03-01), Advani et al.
patent: 4660130 (1987-04-01), Bartley et al.
patent: 4725987 (1988-02-01), Cates
patent: 4777591 (1988-10-01), Chang et al.

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