Electricity: measuring and testing – Fault detecting in electric circuits and of electric components – Of individual circuit component or element
Reexamination Certificate
1999-02-01
2002-03-26
Nguyen, Vinh P. (Department: 2858)
Electricity: measuring and testing
Fault detecting in electric circuits and of electric components
Of individual circuit component or element
C324S765010
Reexamination Certificate
active
06362637
ABSTRACT:
FIELD OF THE INVENTION
This invention relates generally to semiconductor manufacture and more particularly to a method, apparatus and system for testing semiconductor dice contained on a wafer.
BACKGROUND OF THE INVENTION
Semiconductor dice must be tested during the manufacturing process to insure the reliability and performance characteristics of the integrated circuits on the dice. Accordingly, different testing procedures have been developed by semiconductor manufacturers for testing semiconductor dice. Standard tests for gross functionality are typically performed by probe testing the dice at the wafer level. Probe testing at the wafer level can also be used to rate the speed grades of the dice. Probe testing is typically performed using a probe card and wafer stepper.
Burn-in testing is typically performed after the dice have been singulated from the wafer and individually packaged. During burn-in testing, the packaged dice are subjected to temperature cycling for extended periods of time, while different electrical parameters of the integrated circuits are evaluated. For burn-in testing, a testing apparatus such as a burn-in board and burn-in oven can be used.
It would be advantageous to be able to burn-in test the semiconductor dice at the wafer level prior to singulation and packaging of the dice. Such a wafer level test procedure would be particularly advantageous in the manufacture of unpackaged dice. With unpackaged dice, carriers must be provided to temporarily package the singulated bare dice for testing and certification as known good dice (KGD). By burn-in testing the dice at the wafer level, the expense associated with temporarily packaging the bare dice for burn-in would be eliminated.
SUMMARY OF THE INVENTION
In accordance with the invention, a method, apparatus and system for wafer level testing semiconductor dice are provided. The method includes providing a carrier configured to house a semiconductor wafer and to establish electrical communication between the dice on the wafer and testing circuitry. The carrier, generally stated, comprises: a base and a cover for retaining the wafer; an interconnect for establishing temporary electrical communication with the dice on the wafer; and a force applying member for biasing the wafer against the interconnect. The carrier is operable with a testing apparatus having testing circuitry configured to apply test signals through the interconnect to the integrated circuits on the dice. The testing apparatus can include a chamber for subjecting the wafer to temperature cycling during testing of the integrated circuits. The temperature cycling can be heating for burn-in testing, or in some test procedures, cooling the integrated circuits below ambient (e.g., −25° C. to 125° C.).
In an illustrative embodiment the interconnect is interchangeable with other interconnects to allow testing of different wafer configurations using the same carrier. The interconnect includes contact members configured to electrically connect to contact locations, such as flat or bumped bond pads on the wafer. The interconnect can comprise a silicon substrate with etched contact members, or alternately, a substrate having microbump contact members formed on a tape material, similar to multi layered TAB tape. The interconnect can be mounted to the carrier base with the contact members on the interconnect electrically connected to an electrical connector formed on the base. The electrical connector on the carrier base can be configured for making electrical engagement with a corresponding electrical connector on the testing apparatus. An electrical path between the interconnect and the electrical connector can be with TAB tape, impedance matched TAB tape, wire bonds or mechanical-electrical connectors, such as clips or slides.
The force applying member for the carrier can comprise one or more compressible spring members formed of an elastomeric material. In the illustrative embodiment, a first elastomeric spring member is placed in contact with the wafer and cover, and a second elastomeric spring member is placed in contact with the interconnect and base. The dimensions of the carrier and thicknesses of the elastomeric spring members can be selected such that in the assembled carrier, the wafer and interconnect are biased against one another by forces generated by compression of the elastomeric spring members. Alternately the compressible spring member can comprise a gas filled bladder.
For assembling the carrier with a wafer under test (WUT), optical alignment techniques can be used to align the contact locations on the wafer with the contact members on the interconnect. For example, a split optics alignment device, such as an aligner bonder tool, can be used to align the wafer with the interconnect and to place the wafer and the interconnect in contact. During the alignment and assembly process, the wafer can be secured to the cover by applying a vacuum force through a vacuum opening in the cover. With the wafer and interconnect placed in contact, the cover can be secured to the carrier base with a latching mechanism comprising clips, magnets, threaded fasteners or similar members.
In an alternate embodiment the carrier base comprises a board formed of an insulating material, such as a glass filled resin (e.g., FR-4 board), or a ceramic material. In this alternate embodiment, the interconnect can be placed in electrical communication with conductors and an edge connector formed on the base.
In another alternate embodiment, the base and interconnect can comprise a ceramic substrate with deposited conductors and indentation contact members for bumped dice. Interlevel conductors formed in the ceramic substrate electrically connect the indentation contact members to terminal contacts formed on the base. The terminal contacts can comprise ball contacts arranged in a ball grid array (BGA) for high speed testing of wafers having a large number of contact locations (e.g., 1000 or more). In this embodiment the ceramic substrate can also include an edge connector configured for direct electrical connection to a burn-in board. For testing dice with flat bond pads, the substrate can comprises a photo etchable glass formed with etched contact members and deposited conductors.
A system for testing a semiconductor wafer in accordance with the invention can include the wafer carrier and a testing apparatus in electrical communication with test circuitry. During the test procedure defective dice on the wafer can be identified and discarded during a subsequent wafer singulation process. Optionally, if the wafer has a high enough yield of good dice, the wafer carrier and tested wafer can comprise a permanent multi chip module.
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Akram Salman
Farnworth Warren M.
Hembree David R.
Jacobson John O.
Wark James M.
Gratton Stephen A.
Nguyen Vinh P.
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