Apparatus for testing memory device

Static information storage and retrieval – Addressing – Particular decoder or driver circuit

Reexamination Certificate

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C365S201000, C365S200000

Reexamination Certificate

active

07965576

ABSTRACT:
Embodiments relate to an apparatus that may test a memory device. According to embodiments, a period of memory development may be reduced in a manner of testing a delay of a major part in a memory by adding a simple circuit without using expensive equipment and by which a memory development cost can be lowered. According to embodiments, a memory device may include a memory array and a redundancy memory. According to embodiments, a device may include a programmable redundancy decoder determining a drive force to corresponding to a selection signal, the programmable redundancy decoder outputting the determined drive force to a word line of the redundancy memory and a delay difference generating unit generating a delay difference signal corresponding to a delay difference between first and second word line signals outputted from the redundancy memory.

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patent: 7002861 (2006-02-01), Kuo
patent: 7646658 (2010-01-01), Chen et al.
patent: 2008/0117702 (2008-05-01), Henry et al.
patent: 2009/0285047 (2009-11-01), Brown et al.

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