Apparatus for testing integrated circuits using time division mu

Details Apparatus for testing integrated circuits using time division mu Apparatus for testing integrated circuits using time division mu

1993-03-25

1995-05-23

Nguyen, Vinh

Electricity: measuring and testing

Measuring, testing, or sensing electricity, per se

With rotor

324 731, G01R 3128

Patent

active

054184525

ABSTRACT:
An apparatus for observing dedicated test nodes of an integrated circuit (IC) substantially simultaneously while limiting the number of necessary IC pins is provided. The apparatus utilizes time division multiplexing (TDM) to provide a plurality of signals to a logic analyzer from test nodes within an integrated circuit through a single output pin. A multiplexer receives a plurality of signals from IC test nodes and provides an interleaved stream of time slices from each signal on its output. The signals are demultiplexed and reconstructed by the logic analyzer. Sampling of the signals must be fast enough to satisfy the Nyquist criterion for sampling speed. In another embodiment, the apparatus provides a multiplexer hierarchy to increase the total number of observable test nodes. Test node signals which are known to have slow transition rates are grouped and input into a lower-level multiplexer. The output of the lower-level multiplexer is then fed into the input of a higher-level multiplexer which is connected to the logic analyzer.

REFERENCES:
patent: 4956602 (1990-09-01), Parrish
patent: 4961053 (1990-10-01), Krug
patent: 5053700 (1991-10-01), Parrish
patent: 5059899 (1991-10-01), Farnworth et al.
patent: 5241266 (1993-08-01), Ahmad et al.

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