Apparatus for testing dynamic noise immunity of digital integrat

Details Apparatus for testing dynamic noise immunity of digital integrat Apparatus for testing dynamic noise immunity of digital integrat

1982-09-24

1984-11-06

Atkinson, Charles E.

Excavating

324 73R, 371 64, G01R 3128

Patent

active

044816286

ABSTRACT:
Apparatus for testing dynamic noise immunity of digital integrated circuits wherein noise pulses of predetermined duration and amplitude are applied to the inputs of an integrated circuit under test. The tested circuit outputs which normally are at logic level 0 are connected to the inputs of a first group of control logic gates, while the tested circuit outputs which normally are at logic level 1 are connected to the inputs of a second group of control logic gates. The outputs of such groups feed a fault detection circuit. The input voltage thresholds of control logic gates is adjusted by suitable circuits so as to check the dynamic noise immunity of the integrated circuit under test for a predetermined logic swing.

REFERENCES:
patent: 3541441 (1970-11-01), Hrustich
patent: 3548176 (1970-12-01), Shutler
patent: 3573445 (1971-04-01), Korytnaja et al.
patent: 4125764 (1978-11-01), Chambers et al.

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