Electricity: measuring and testing – Fault detecting in electric circuits and of electric components – Of individual circuit component or element
Reexamination Certificate
1999-02-12
2002-06-25
Sherry, Michael J. (Department: 2829)
Electricity: measuring and testing
Fault detecting in electric circuits and of electric components
Of individual circuit component or element
Reexamination Certificate
active
06411115
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a testing circuit/method for a semiconductor device.
2. Description of the Related Art
There is a testing circuit/method called a boundary scan for testing connection of a semiconductor device with an external equipment or another semiconductor device. The boundary scan is a testing circuit/method for a semiconductor device provided in the IEEE Standard 1149.1.
The boundary scan testing circuit has the following control terminals; a clock terminal for the boundary scan testing, a terminal of a control register for controlling state transition in a test, serial data input terminals for individual data registers, an initialization terminal for the control register and serial data output terminals from individual data registers.
An exclusive buffer for the boundary scan testing circuit has a function of disconnecting with an internal circuit by the control register to present an output to the data register, or receiving the data set in the data register to output them to an external equipment. The exclusive buffer also has, besides data input/output, a function of forming a high impedance state.
The data register of the boundary scan testing circuit has a function of retaining data from the exclusive buffer register or data to the exclusive buffer by the control resister. Also, individual data registers are connected in serial to each other to transmit their data to a subsequent data register.
The control register of the boundary scan testing circuit controls the exclusive buffer and the data register for achieving a predetermined test mode.
A boundary-scan testing method using such a testing circuit sets measured data in a data register of a semiconductor device which is placed upstream of a tested semiconductor device and then performs observation with the data register of the tested semiconductor device for ensuring that correct data are transmitted.
The test method has the following states;
EXTEST mode for testing connection between semiconductor devices,
SAMPLE mode for measuring output data from a tested semiconductor device,
BYPASS mode for setting a test mode or data for the data register, skipping a given semiconductor device, and
CLAMPIO mode for setting all output terminals of a semiconductor device to a high impedance state.
However, in the testing circuit of the prior art, an exclusive buffer and a data register are placed between an internal circuit of a tested semiconductor device and an external terminal. It can, therefore, test only signal terminals, but not whether power and GND terminals essential for operating the semiconductor device are correctly connected.
SUMMARY OF THE INVENTION
An objective of this invention is to provide a testing circuit/process for a semiconductor device, which can conveniently test connection states of power and GND terminals to improve reliability of the device.
This invention provides a testing circuit for a semiconductor device comprising a plurality of external terminals; a plurality of external terminal wires, each of which is connected to one of the external terminals; a testing external terminal; a testing wire connected to the testing external terminal; a plurality of switches placed between the testing wire and the external terminal wires; and a control circuit for selecting one of the switches to bring it into conduct, in response to a test signal.
This invention also provides a semiconductor device into which the above testing circuit is built.
This invention also provides a testing process for a semiconductor device into which the above testing circuit is built, comprising, when testing a power terminal as the external terminal, the steps of applying a lower voltage to the testing external terminal than that to the power terminal and bringing a selected switch corresponding the tested power terminal into conduct by the control circuit while measuring a potential of the tested external terminal, which are repeated for individual power terminals; and, when testing a GND terminal as the external terminal, the steps of applying a voltage to the testing external terminal and bringing a selected switch corresponding the tested GND terminal into conduct by the control circuit while measuring a potential of the tested external terminal, which are repeated for individual GND terminals.
This invention allows one to test whether power terminals of a semiconductor device are correctly connected. It is because a power wire is divided into parts corresponding to individual power terminals to permit a power terminal separated from an internal circuit to be freely selected and a potential of the tested external terminal may be measured to readily determine correctly and incorrectly connected terminals.
This invention also allows one to test whether GND terminals of the semiconductor device are correctly connected. It is because the GND wire is divided into parts corresponding to individual GND terminals to permit a GND terminal separated from an internal circuit to be freely selected and a potential of the tested external terminal may be measured to readily determine correctly and incorrectly connected terminals.
This invention also allows one to individually test and determine connection states for power or GND terminals. It is because the power or GND terminals which are usually connected through a common power or GND wire are separated to independently test each terminal.
REFERENCES:
patent: 3849872 (1974-11-01), Hubacher
patent: 4843314 (1989-06-01), Barnaby
patent: 5164663 (1992-11-01), Alcorn
patent: 5442282 (1995-08-01), Rostoker et al.
patent: 5640102 (1997-06-01), Sato
patent: 5744949 (1998-04-01), Whetsel
patent: 5898703 (1999-04-01), Lin
patent: 9-26463 (1997-01-01), None
patent: 10-288647 (1998-10-01), None
Kobert Russell M.
Scully Scott Murphy & Presser
Sherry Michael J.
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