Excavating
Patent
1991-12-18
1993-07-27
Anderson, Lawrence E.
Excavating
395575, 395375, 395800, 364DIG1, 3642449, 3642653, 3642664, G06F 1100
Patent
active
052316378
ABSTRACT:
A test circuit for testing a programmable array of a microprocessor including an instruction register for receiving an instruction signal from a data bus in response to a control signal and for outputting the received instruction signal to output lines, and a programmable logic array having a plurality of NAND circuits each forming a conductive path between first and second terminals when a predetermined instruction signal is received thereby from the register. Each of the NAND circuits includes a first terminal, a second terminal and a plurality of MOSFETs each having a first, a second and a gate electrode with the gate electrode coupled to an output line of the instruction register, and with the first and second electrodes being connected in series between the respective first and second terminals. A first precharge circuit is coupled to the first terminal of the NAND circuits, to a test terminal for providing a test signal and to a precharge terminal for providing a precharge signal, with this first precharge circuit supplying a first potential level to the first terminal of the NAND circuits in response to either the precharge signal or the test signal. A second precharge circuit is coupled to the second terminal of the NAND circuits, to the precharge terminal and to a power supply terminal for supplying a second potential level, with the second precharge circuit supplying the second potential level to the second terminal of the NAND circuits in response to the precharge signal. The current flowing through the power supply terminal, and thus through a conductive NAND circuit or circuits when the first and second potential levels are present, can then be measured to test the array.
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Anderson Lawrence E.
Ellis Richard Lee
OKI Electric Industry Co., Ltd.
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