Oscillators – Automatic frequency stabilization using a phase or frequency... – With intermittent comparison controls
Patent
1999-05-26
2000-11-14
Mis, David
Oscillators
Automatic frequency stabilization using a phase or frequency...
With intermittent comparison controls
331 11, 331 12, 331 17, 331 25, 327147, 327298, H03L 706, H03L 707, H03L 7085
Patent
active
061475629
DESCRIPTION:
BRIEF SUMMARY
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention related generally to a synchronization unit for synchronizing two system clocks in an electronic device, such as a switching device.
2. Description of the Related Art
For satisfying increased operational dependability in switching technology, it is demanded that two processor assemblies (one of the two is a master and the other is a slave) work redundantly. This can be achieved by micro-synchronous operation, whereby the slave synchronizes to the master. The master in turn synchronizes to an external reference clock. Given an outage of the external reference clock, the (clock) master must continue to work for example, in a (hold over mode) and the slave must continue to synchronize to the master.
The critical demand for micro-synchronous operation is that the phase difference between the two processor assemblies should lie within an extremely slight time difference (for example, 5 ns).
Synchronization methods wherein phase information are exchanged between the two processor assemblies can be imagined for satisfying the demand. In these methods, however, falsifications of the phase information can occur due to different gate running times and reflections on the connecting lines between the two assemblies. This leads to operating instabilities.
The European patent document EP 0 175 888 A discloses a synchronization means using a phase comparator with each incoming channel to compare the clock phase of the incoming signal and a local oscillator. The phase comparator of the active unit generates a signal to control the oscillator to maintain its output in phase with incoming signal. The oscillator is a voltage controlled quartz oscillator.
SUMMARY OF THE INVENTION
The present invention is based on the object of providing a synchronization portion of an assembly that meets the demand for collaboration with the synchronization portion of a partner assembly.
This object is achieved by a synchronization portion of an assembly that generates the system clock of the assembly, whereby it synchronizes the system clock to one of several existing reference clocks, including, signal applied to its control input; and is present respectively once per reference clock signal, whereby a respective reference clock signal is applied to one input of a phase detector and the system clock is respectively applied to the other input; such that respectively one of the output signals of the filters is through-connected to the control input of the VCO, the operating control controls further switches such that, given the arrangement wherein the output signal of the filter is not through-connected to the input of the VCO, other filter input.
One embodiment of the invention provides a delay unit that delays the system clock before the input to the phase detector by the running time difference between reference clock and system clock which makes it possible to switch the mode of a processor assembly (for example, from clock master to clock slave or vice versa) without leaving the micro-synchronous operation (slave/slave is not possible). The switching is thus possible during micro-synchronous operation.
BRIEF DESCRIPTION OF THE DRAWINGS
An exemplary embodiment of the invention is explained in greater detail below with reference to the drawings.
FIG. 1 is a block diagram showing the synchronization system of the present invention in a master/slave processor arrangement;
FIG. 2 is functional block diagram of the synchronization portion;
FIG. 3 is a circuit diagram showing the activated operating mode;
FIG. 4 is a circuit diagram showing the standby mode; and
FIG. 5 is a circuit diagram showing the circuit in the monitor mode.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
FIG. 1 shows the basic structure of the mutual clock synchronization. According to the illustrated structure, a respective PLL is contained in an assembly, a switch that serves for switching between the operating modes "Master" and "Slave" of an assembly being present at the input there
REFERENCES:
patent: 4511859 (1985-04-01), Dombrowski
patent: 5216387 (1993-06-01), Telewski et al.
patent: 5739727 (1998-04-01), Lofter et al.
Mis David
Siemens Aktiengesellschaft
LandOfFree
Apparatus for synchronizing master and slave processors does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Apparatus for synchronizing master and slave processors, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Apparatus for synchronizing master and slave processors will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2068886