Apparatus for symmetrically truncating two's complement binary s

Details Apparatus for symmetrically truncating two's complement binary s Apparatus for symmetrically truncating two's complement binary s

1983-05-16

1986-05-13

Thomas, James D.

Boots, shoes, and leggings

358 31, G06F 738, H04N 964

Patent

active

045890846

ABSTRACT:
Symmetrical truncation of two's complement binary numbers is performed by simply discarding the LSB's of positive values and by adding "one" to the truncated negative value when any one of the discarded LSB's is a logical "one" value. Apparatus to perform an N bit truncation includes an incrementer, a two input AND gate and an N-input OR gate.

REFERENCES:
patent: 4034196 (1977-07-01), Butterweck et al.
patent: 4034197 (1977-07-01), Lawrence et al.
patent: 4095276 (1978-06-01), Verkroost et al.
patent: 4195350 (1980-03-01), Moore
patent: 4280190 (1981-07-01), Smith
patent: 4340940 (1982-07-01), Williams, Jr. et al.
T. Fischer, "Digital VLSI Breeds Next-Generation TV Receivers", Electronics, Aug. 11, 1981, pp. 97-103.

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