Apparatus for symmetrically reducing N least significant bits of

Details Apparatus for symmetrically reducing N least significant bits of Apparatus for symmetrically reducing N least significant bits of

1995-12-29

1997-12-09

Mai, Tan V.

Boots, shoes, and leggings

G06F 738

Patent

active

056967101

ABSTRACT:
An M-bit digital signal, the most significant bit (MSB) thereof and an integer K are added to produce a sum which is truncated by N least significant bits to provide a symmetrically rounded bit-reduced digital output signal. The MSB may be applied in true or complemented form to the adder for selecting wide or narrow rounding modes having different numbers of output zeros disposed about a point of symmetry for a given input signal change. Advantageously, undesirable direct current (DC) shifts due to least significant bit (LSB) reduction in digital video, audio or similar applications are prevented.

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