Apparatus for suspending the bus cycle of a microprocessor by in

Details Apparatus for suspending the bus cycle of a microprocessor by in Apparatus for suspending the bus cycle of a microprocessor by in

1993-12-17

1996-12-03

Barry, Esq., Lance Leonard

395494, 395879, G06F 1300

Patent

active

055817459

ABSTRACT:
An interrupt request processing device and method for control of the bus cycle of a microprocessor which implements predetermined wait periods dependent upon a detected wait request. Predetermined wait states, programmable in the microprocessor, are assigned to wait request signals for implementation of a predetermined wait period corresponding to a detected wait request signal, in which the bus cycle is suspended for the predetermined wait period while the signal to be applied to the connected peripheral device is held during access to the peripheral device. After the predetermined wait period is over the bus cycle is unsuspended and the microprocessor is again able to detect wait request signals.

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