Apparatus for suppressing an error report from an address for wh

Details Apparatus for suppressing an error report from an address for wh Apparatus for suppressing an error report from an address for wh

1990-10-01

1993-07-06

Atkinson, Charles E.

Boots, shoes, and leggings

36424341, 3642653, 364DIG1, 3649642, 364DIG2, 371 216, G06F 1100

Patent

active

052261506

ABSTRACT:
A write-back cache memory system is disclosed which includes a source of a sequence of memory addresses and a tag store coupled to the source of addresses and accessed by an index portion of said addresses, which produces information relating to the addresses. The write-back cache memory system also includes an error detector for detecting an error in the tag store information. Circuitry is included for reporting an error and saving the index which caused the error if an error is detected but no error has been previously detected. Comparing circuitry is included for comparing the index causing the current error to the previously saved address if an error is detected and an error has been previously detected; and if the address is not the same, then reporting a fatal error; otherwise, if the index is the same, then not reporting a fatal error.

REFERENCES:
patent: 4939641 (1990-07-01), Schwartz et al.
patent: 5119485 (1992-06-01), Ledbetter, Jr. et al.
patent: 5148533 (1992-09-01), Joyce et al.

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