Electrical computers and digital processing systems: processing – Architecture based instruction processing
Reexamination Certificate
2006-01-31
2006-01-31
Kim, Kenneth S. (Department: 2111)
Electrical computers and digital processing systems: processing
Architecture based instruction processing
C712S043000, C712S229000, C718S102000
Reexamination Certificate
active
06993640
ABSTRACT:
A processor supports logical partitioning of hardware resources including real address spaces of a computer system. An ultra-privileged supervisor process, called a hypervisor, regulates the logical partitions and can dynamically re-allocate resources. Preferably, the processor supports hardware multithreading, each thread independently capable of being in either hypervisor, supervisor, or problem state, and is capable of entering hypervisor state only upon occurrence of certain pre-defined events. A logical partition identifier is stored in a processor register, and can be altered by the processor only when in hypervisor state. Certain bus communications contain a logical partition identifier tag, and the processor ignores such communications if the tag does not match its own logical partition identifier in its register.
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Doing Richard William
Kalla Ronald Nick
Schwinn Stephen Joseph
Silha Edward John
Tsuchiya Kenichi
Kim Kenneth S.
Truelson Roy W.
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