Apparatus for strictly ordered input/output operations for inter

Details Apparatus for strictly ordered input/output operations for inter Apparatus for strictly ordered input/output operations for inter

1992-10-02

1994-11-22

MacDonald, Allen R.

Boots, shoes, and leggings

395550, 3642716, 3642717, 364DIG1, G06F 900

Patent

active

053676890

ABSTRACT:
A method and apparatus which maintains strict ordering of processor cycles to guarantee that a processor write, such as an EOI instruction, is not executed to the interrupt controller prior to the interrupt request from a requesting device being cleared at the interrupt controller, thus maintaining system integrity. Interrupt controller logic is included on each respective CPU board. The processor can access the interrupt controller over a local bus without having to access the host bus or the expansion bus and thus an interrupt controller access could be completed before a previously generated I/O cycle has completed. Therefore, the apparatus which tracks expansion bus cycles and interrupt controller accesses and maintains strict ordering of these cycles to guarantee that an interrupt request is cleared at the interrupt controller prior to execution of write operation to the interrupt controller.

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Japanese Abstract, Publication No. JP59052324, dated Mar. 26, 1984, Entitled Detecting Circuit For Service Interruption And Its Recovery.
Method Of Keeping Distributed Interrupt Requests Consistent, IBM Technical Disclosure Bulletin, vol. 33, No. 11, Apr. 1991, pp. 208-209.
Method Of Improving Parallel Port Interrupts In Personal Computers, IBM Technical Disclosure Bulletin, vol. 35, No. 1A, Jun. 1992, pp. 54-58.

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