Apparatus for SRAM array power reduction through majority...

Details Apparatus for SRAM array power reduction through majority... Apparatus for SRAM array power reduction through majority...

2006-12-12

2008-12-23

Ho, Hoai V. (Department: 2827)

Static information storage and retrieval

Powering

Conservation of power

C365S189070, C365S154000

Reexamination Certificate

active

07468929

ABSTRACT:
A mechanism for reducing the amount of power or energy consumed by an SRAM array when the SRAM array is being accessed is provided. Logic is provided that identifies a polarity of a row of memory cells whose data values are to be read. The polarity of the row of memory cells indicates whether a majority of the data values stored in the row of memory cells are logic 1 data values or logic 0 data values. Based on the polarity, selection logic either selects true data values or complement data values of the memory cells. Additional logic is provided in each memory cell for outputting a true data value to a read bit line and outputting a compliment data value to the read bit line based on the polarity.

REFERENCES:
patent: 2005/0018519 (2005-01-01), Nii
patent: 2002366419 (2002-12-01), None
Chang et al., “Conforming Block Inversion for Low Power Memory”, IEEE, Transactions on Very Large Scale Integration (VLSI) Systems, vol. 10, No. 1, Feb. 2002, pp. 15-19.

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