Patent
1994-10-24
1997-04-29
Ellis, Richard L.
395394, G06F 934
Patent
active
056257899
ABSTRACT:
An apparatus performs source operand dependency analysis, perform register renaming and provide rapid pipeline recovery for a microprocessor capable of issuing and executing multiple instructions out-of-order in a single machine cycle. The apparatus first provides an enhanced means for rapid pipeline recovery due to a mispredicted branch or other store/load conflict or unsupported store/load forward circumstances. Second, the apparatus provides an improved instruction scheduling means wherein the oldest instructions that have all of their dependencies resolved are executed first. Third, the apparatus provides a means for enabling any execution or memory access instruction to execute out-of-order. Fourth, the apparatus provides a means for handling precise recovery of interrupts when processing instructions in out-of-order sequence.
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Ciavaglia Stephen J.
Esling Walter T.
Hesson James H.
LeBlanc Jay
Wilcox Pamela A.
Blecker Ira D.
Ellis Richard L.
International Business Machines - Corporation
Patel Gautam R.
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