Apparatus for simultaneously scheduling instruction from plural

Details Apparatus for simultaneously scheduling instruction from plural Apparatus for simultaneously scheduling instruction from plural

1992-06-04

1995-07-04

Lall, Parshotam S.

Boots, shoes, and leggings

364DIG1, G06F 938

Patent

active

054308518

ABSTRACT:
Disclosed is an information processor comprising multiple instruction setup units which fetch and decode instructions as the first half of the procedure in instruction pipelines, each of the instruction setup units being in charge of processing instruction streams. The decoded results are scheduled in instruction schedule units and sent to each corresponding function unit to be executed.

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MC88100 RISC Microprocessor User's Manual, Motorola 1990.
SPARC RISC User's Guide, Ross Technology, Inc. A Cypress Semiconductor Company, 1990.
Am29000 Streamlined Instruction Processor User's Manual, Advanced Micro Devices, 1987.

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