Television – Bandwidth reduction system – Data rate reduction
Patent
1995-12-28
1998-09-08
Powell, Mark R.
Television
Bandwidth reduction system
Data rate reduction
348427, 348441, H04N 712
Patent
active
058052291
ABSTRACT:
An apparatus converts a subsampled video frame signal into an interpolated original video signal with a improved computational speed by using: a zero stuffing circuit for generating the (N+1)/2 video line signals alternately decimated; a first interpolation circuit for generating an interpolated even video line signal; a second interpolation circuit for generating an interpolated odd video line signal; and delay lines for simultaneously coupling the (N+1)/2 video line signals to the first and the second interpolation circuits to thereby allow the simultaneous generation of the interpolated even and odd video line signals.
REFERENCES:
patent: 4608600 (1986-08-01), Sugiyama
patent: 4866519 (1989-09-01), Lucas et al.
patent: 5151783 (1992-09-01), Faroudja
patent: 5307164 (1994-04-01), Dong-Il
patent: 5337089 (1994-08-01), Fisch
Christophe Joanblanq et al "A 54MHz CMOS Programmable Video Signal Processor for HDTV Applications", IEEE Journal of Solid-State Circuits, 25, No. 3, pp. 730-734, Jun. 1990.
Daewoo Electronics Co. Ltd.
Miller John W.
Powell Mark R.
LandOfFree
Apparatus for simultaneously generating interpolated video signa does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Apparatus for simultaneously generating interpolated video signa, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Apparatus for simultaneously generating interpolated video signa will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-1287173