Apparatus for setting write latency

Details Apparatus for setting write latency Apparatus for setting write latency

2002-08-29

2004-02-24

Le, Thong (Department: 2818)

Static information storage and retrieval

Addressing

Sync/clocking

C365S194000, C365S189040

Reexamination Certificate

active

06697297

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to a method and apparatus for setting write latency in a memory system. More particularly, the present invention relates to a write latency procedure and apparatus which reduce the risk of data stored in memory being defective due to the memory improperly receiving a write enable (RxEn) signal too early or too late in relation to the data and the preamble of the data clock to compensate for timing variations occurring after initialization.
2. State of the Art
Many integrated circuits and electronic devices use memory systems for storing data. Over time, the need for smaller and faster circuits and devices has reduced the tolerance for error, particularly in data transfer systems. Errors in a data storage system slow the system by requiring additional data transfer or causing the system to use unreliable or incorrect data.
The data transmission rate of modem integrated circuits is primarily limited by internal circuitry operating speeds. That is, communication networks have been developed which can transmit signals between circuitry at a rate that is faster than the capacity of many integrated circuits. To address the need for faster circuits, a group of integrated circuits can be on a common bus. In this configuration, each integrated circuit operates in a coordinated manner with the other integrated circuits to share data which is transmitted at a high speed. An example of such a high-speed data system is described in U.S. Pat. No. 5,917,760 to Millar (Jun. 29, 1999), incorporated herein by reference. Millar describes a high-speed data system using a common bus and a memory subsystem commonly known as SyncLink dynamic random access memory (“SLDRAM”). By providing an appropriate number of memory devices and an efficient control system as used in SLDRAM, very high-speed data transmission can be achieved.
In computer memory systems, particularly in what is often termed the main memory, information is typically stored in dynamic random access memory (“DRAM”) integrated circuits. A memory controller manages the operations of the DRAMs. Some of the operations which are managed by the memory controller for DRAMs are read and write operations. A read operation of a memory controller typically includes the following steps: 1) initiating, via the memory controller, the read operation; 2) generating the row address strobe/column address strobe (RAS/CAS) memory timing signals and applying them, to the memory bank targeted by the read operation; 3) once the read data is available on the bank's memory data bus, buffering the read data into a buffer coupled to the memory bank; and 4) transferring the data from the memory buffer into a data path buffer for storage until the data is placed onto the processor bus for transmission to the processor or device requesting the data. In synchronous read operations such as those performed in SLDRAM, an output of data on the data bus results from a read command and an address received at a preceding leading edge of the clock. The delay in the number of clock cycles between the arrival of the read command at the input to the control logic and the availability of data at the data bus is the “latency” of the DRAM. In other words, the memory controller sends a read command to the DRAM based upon the latency setting which is programmed into the DRAM as part of an initialization process. The DRAM accesses its own stored data and returns the requested data at the appropriate time.
Distinct from a read operation, in a write operation the data is not yet stored in the DRAM. Therefore, upon receiving a write command, the DRAM must know ahead of time when the data will arrive in relation to the write command so that it can begin write operations at the correct time. The delay in clock cycles from the arrival of the write command to the beginning of the data is the write latency. A clock “tick” is one-half of a clock cycle, meaning that a clock cycle is the duration between the beginning of a clock cycle to the beginning of the next full clock cycle and a clock tick is only the duration between a falling and a rising (or a rising and a falling) edge of the clock signal. Because the DRAM is dependent upon surrounding systems for supplying both the write command and the data to be written, the latency setting is crucial to obtaining accurate data storage. In response to the write command, the DRAM generates a write enable (RxEn) signal based upon the latency setting. If the internally generated write enable (RxEn) signal fires too far ahead of the data to be written or too close to the data, data may be missed, or incorrect data may be stored. In either case, poor latency settings create reliability and efficiency problems. A write operation typically includes the following steps: 1) transferring the write data from the data path in the memory subsystem to a specified memory device; 2) initiating, via the memory controller, the write operation; and 3) internally generating the necessary memory timing signals and applying them to complete the write operation.
Latency settings in a memory system are established during initialization wherein the data transfer and data receive rates and timing are evaluated so that the subsystems can interfunction with other subsystems by reference to a common clock rate. The latency settings remain unchanged by the system until another initialization process is performed. During initialization of a memory system, the latency for DRAM is set to optimize system performance and to match up the DRAM latency to that expected by the memory controller. After latency settings are chosen during initialization of a system, the system typically changes to a normal operating mode wherein the read and write functions of the memory can be carried out.
In SLDRAM memory systems, there are primarily two methods used for establishing write latency. The first method involves performing a series of sequential writes to and reads from memory address locations while varying the write latency in the SLDRAM or the memory controller for each sequential write. The read and write data are then compared to determine which write latency settings for the SLDRAM match a write latency setting for the memory controller, resulting in valid data. When all of the address locations are read back, good data indicates a match between the DRAM write latency and that of the memory controller. The second method involves a long succession of back-to-back writes to varied address locations performed in a walking pattern. For each new write, the memory controller presents the data and data clock signal (“DCLK”) to the data bus one tick later than the previous write. This allows the write data to “walk” through the point at which the DRAM enables its input buffers. Whenever the data and DCLK signals correctly align with the receiver enable signal, the write operation will capture and store the data correctly. The data at each memory address is then read back starting at the first write address. By analyzing the data pattern at each memory address, the amount of offset between the SLDRAM's and the memory controller's write latencies can be determined and set appropriately.
With reference to
FIG. 1
, in either of the above two methods, a valid write latency setting is indicated when the write enable (RxEn) signal
2
, also called the receiver enable signal, transitions at the SLDRAM receiver
4
, shown in
FIG. 2
, during the low preamble
6
of the DCLK signal
8
. The preamble period is typically either two or three ticks in duration.
FIG. 1
shows a three-tick preamble
6
, meaning the DCLK signal
8
is low for a duration of three clock ticks. Two-tick preambles are also common. If the RxEn signal
2
transitions within the preamble
6
, the SLDRAM will be able to accurately receive and store the data within the oscillation portion
10
of the DCLK signal
8
. However, if the RxEn signal
2
transitions before or after the preamble period, the DRAM will capture data in

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