Apparatus for self checking of functional redundancy check (FRC)

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371 3, G06F 1116

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049032704

ABSTRACT:
An integrated circuit module (200) in which an error detection circuit (234, 263) compares data (204) generated internally on module (200) with data (108) generated externally from another substantially identical module (100). An error detect output (238) is asserted upon the condition that data (204) generated internally on module (200) and data (108) generated externally from module (100) do not match. A circuit (222, 224) alters the internally generated data (204) by injecting erroneous data into the internally generated data (204) to thereby generate altered data (230). Error anticipation control logic (210) generates a test condition (214, 216), which corresponds to the expected error condition caused by altered data. Comparison circuit (242) compares the actual error detect output (238, 240) with expected error detect output (214, 215). An error output (244) is asserted if the actual error detect output (238, 240) and the expected error detect output (214, 216) do not match.

REFERENCES:
patent: 3257546 (1966-06-01), McGovern
patent: 3680069 (1972-07-01), Neumann
patent: 4012717 (1977-03-01), Censier
patent: 4792955 (1988-12-01), Johnson
IBM TDB, "Error-Handling Testing Via Error Injection", vol. 29, No. 2, 7/1986, pp 542-543.
J. M. Baron, "Checking of Check Circuitry", IBM TDB, vol. 11, No. 11, 4/1969, pp 1398-1399.
IBM TDB, "Verification of Error Correction Circuitry", vol. 31, No. 1, 6/1988, pp 127-128.
D. East, "Error Injector for Testing a Data Processing Unit", IBM TDB, vol. 17, No. 6, 11/1974.

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