Active solid-state devices (e.g. – transistors – solid-state diode – Integrated circuit structure with electrically isolated... – Passive components in ics
Reexamination Certificate
2001-03-22
2004-11-23
Wilson, Allan R. (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Integrated circuit structure with electrically isolated...
Passive components in ics
C257S534000, C257S638000, C257S665000, C438S132000
Reexamination Certificate
active
06822309
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of and an apparatus for cutting off a fuse electrode, an integrated circuit device with such a fuse electrode, and a method of manufacturing such an integrated circuit device.
2. Description of the Related Art
Various integrated circuit devices are presently used for various applications. For example, semiconductor memories such as RAMs (Random Access Memories) are used to temporarily store digital data. While attempts have been made to make such semiconductor memories greater in storage capacity and integration level, it is difficult to manufacture highly integrated semiconductor memories of large storage capacity with less defective ratio.
In view of such a difficulty, it has generally been customary at present to include spare memory cells in a semiconductor memory and replace a memory cell that has been found defective with a spare memory cell.
For example, spare word lines and a fuse ROM (Read Only Memory) are provided in advance in a semiconductor memory, and the fuse ROM stores the addresses of defective word lines and spare word lines. When address data supplied from an external source is decoded into a word address, the word address is compared with the addresses of defective word lines stored in the fuse ROM. If the word address agrees with the address of a defective word line, then a spare word line to replace the defective word line is activated.
An integrated circuit device with such a fuse ROM will be described below with reference to
FIGS. 1A-1C
through
4
A-
4
D of the accompanying drawings. X and Y directions referred to hereinbelow are directions extending parallel to the surface of a circuit substrate and perpendicularly to each other, as shown in
FIG. 1A
, and a Z direction referred to hereinbelow is a direction extending perpendicularly to the X and Y directions. Integrated circuit device
100
which is illustrated comprises a semiconductor memory such as a RAM, for example, and, as shown in
FIG. 3D
, comprises fuse ROM
101
and logic circuit
102
which are mounted on one circuit substrate.
Logic circuit
102
comprises a peripheral circuit such as an address decoder and is constructed using wiring patterns in multiple layers. As shown in FIG.
4
D, first wiring pattern
111
is disposed on the surface of isolating layer (or an element isolation region)
110
, and first interlayer insulating film
114
is placed as a cover layer on first wiring pattern
111
. Second wiring pattern
112
is disposed on the surface of first interlayer insulating film
114
, and second interlayer insulating film
115
is placed as a cover layer on second wiring pattern
112
. Third wiring pattern
113
is disposed on the surface of second interlayer insulating film
115
, and passivation film
116
and polyimide film
117
are successively placed as a cover layer on third wiring pattern
113
.
As shown in
FIG. 4A
, first interlayer insulating film
114
has contact hole
119
filled with a conductor that interconnects first wiring pattern
111
and second wiring pattern
112
. Similarly, as shown in
FIG. 4B
, second interlayer insulating film
115
has contact hole
120
filled with a conductor that interconnects second wiring pattern
112
and third wiring pattern
113
.
Passivation film
116
and polyimide film
117
have contact hole
121
defined therein through which third wiring pattern
113
is exposed for use as a bonding pad, for example.
As shown in
FIGS. 1A-1C
, fuse ROM
101
has a plurality of fuse electrodes
130
extending in the X direction and arrayed parallel to each other in the Y direction. As shown in
FIG. 3D
, fuse electrodes
130
are disposed on the surface of isolating layer
110
, and the various films ranging from first interlayer insulating film
114
to polyimide film
117
are successively disposed on fuse electrodes
130
.
Central regions of fuse electrodes
130
in the X direction are defined as a cutting position, and window
131
is defined over the central regions of fuse electrodes
130
.
As shown in
FIG. 3D
, window
131
is in the form of a recess defined in the films and extending from the surface of polyimide film
117
to a middle position in first interlayer insulating film
114
. In window
131
, only first interlayer insulating film
114
remains as a layer of a thickness of about 200 (nm) over fuse electrodes
130
.
As shown in
FIG. 2
, a laser beam emitted downwardly in the Z direction from an upper laser beam source is applied to fuse electrodes
130
of fuse ROM
101
, cutting off desired fuse electrodes
130
thereby to record address data, etc. in fuse ROM
101
.
A process of manufacturing integrated circuit device
100
will be described below with reference to
FIGS. 3A-3D
and
FIGS. 4A-4D
.
FIGS. 3A-3D
correspond respectively to
FIGS. 4A-4D
.
As shown in
FIGS. 3A and 4A
, first wiring pattern
111
of logic circuit
102
and fuse electrodes
130
of fuse ROM
101
are deposited as an aluminum layer having a thickness of 0.32 (&mgr;m) on the surface of isolating layer
110
. Then, first interlayer insulating film
114
of SiO
2
or NSG (Nondope Silicate Glass) having a thickness of about 0.5 (&mgr;m) is grown on the entire surface of isolating layer
110
.
Thereafter, contact hole
119
extending to first wiring pattern
111
is defined in first interlayer insulating film
114
, and second wiring pattern
112
connected to first wiring pattern
111
via contact hole
119
is deposited as an aluminum layer having a thickness of 0.32 (&mgr;m) on the surface of first interlayer insulating film
114
.
Then, second interlayer insulating film
115
of SiO
2
or NSG having a thickness of about 1.0 (&mgr;m) is grown on the entire surface of first interlayer insulating film
114
. As shown in
FIGS. 3B and 4B
, contact hole
120
extending to second wiring pattern
112
is defined in second interlayer insulating film
115
. Recess
132
is defined in second interlayer insulating film
115
at the position of window
131
of fuse ROM
101
, leaving a layer of second interlayer insulating film
115
having a thickness of about 1300 (nm) in an upper portion of fuse ROM
101
.
Then, as shown in
FIGS. 3C and 4C
, third wiring pattern
113
connected to second wiring pattern
112
via contact hole
120
is deposited as an aluminum layer having a thickness of 0.80 (&mgr;m) on the surface of second interlayer insulating film
115
. Passivation film
116
of SiN having a thickness of about 1.0 (&mgr;m) and polyimide film
117
having a thickness of about 6.0 (&mgr;m) are successively grown on the entire surface of second interlayer insulating film
115
.
As shown in
FIGS. 3D and 4D
, large-size contact hole
121
extending to the surface of third wiring pattern
113
and window
131
of fuse ROM
101
are defined in passivation film
116
and polyimide film
117
, leaving a layer of polyimide film
117
and passivation film
116
having a thickness of about 200 (nm) in the upper portion of fuse ROM
101
.
According to the above process of manufacturing integrated circuit device
100
, fuse electrodes
130
and first wiring pattern
111
can be fabricated in one step, and contact holes
120
,
121
and window
131
can be defined in one step. Therefore, fuse ROM
101
and logic circuit
102
can be produced simultaneously.
In integrated circuit device
100
, as described above, desired ones of plural fuse electrodes
130
arrayed in the Y direction are cut off by a laser beam to record desired data in fuse ROM
101
.
When fuse electrodes
130
are cut off by the laser beam, their components are melted and scattered around. No problem arises from scattered fragments of the components if only one fuse electrode
130
is cut off and adjacent fuse electrodes
130
are not cut off, as indicated by an area A in FIG.
2
. However, if adjacent fuse electrodes
130
are cut off, as indicated by an area B in
FIG. 2
, then they may be short-circuited by scattered fragments of the components.
Fuse ROM
101
is also required to be increased
NEC Electronics Corporation
Sughrue & Mion, PLLC
Warren Matthew
Wilson Allan R.
LandOfFree
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