Apparatus for selecting bank in semiconductor memory device

Details Apparatus for selecting bank in semiconductor memory device Apparatus for selecting bank in semiconductor memory device

2001-12-28

2003-05-27

Nguyen, Viet Q. (Department: 2818)

Static information storage and retrieval

Addressing

Multiplexing

C365S230010, C365S230040, C365S230060, C365S225700, C365S230030

Reexamination Certificate

active

06570808

ABSTRACT:

RELATED APPLICATION
The present application claims the benefit of Korean Application No. 87292/2000 filed Dec. 30, 2000, under 35 U.S.C. §119, which is herein fully incorporated by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device including a plurality of memory banks, and more particularly, to an apparatus and method for selecting banks in a semiconductor memory device to provide a half memory capacity product (hereinafter “half-chip”) even when a failure occurs in a plurality of banks divided into upper and lower blocks.
2. Discussion of the Related Art
Memory banks (“banks”) are sections of a memory device that store data and information.
FIG. 1
shows an apparatus
30
for selecting banks in a semiconductor memory device according to a related art, in which the structure of a direct Rambus DRAM of 32 banks and 128M is shown in part.
Referring to
FIG. 1
, the bank selecting apparatus
30
is connected between a lower bank block
10
having first to sixteenth banks and an upper bank block
20
having seventeenth to thirty-second banks. The bank selecting apparatus
30
receives bank address bits BKADDR
0
to BKADDR
4
(together representing addresses) to select
32
banks. The appropriate bits BKADDR
0
to BKADDR
4
are input to the apparatus
30
from an external source or other internal source. If a logic value of the most upper bank address bit BKADDR
4
input thereto is ‘0’, then the bank selecting appartus
30
selects the lower bank block
10
. If a logic value of the most upper bank address bit BKADDR
4
is ‘1’, then the bank selecting apparatus
30
selects the upper bank block
20
.
The bank selecting apparatus
30
includes fuses F
1
and F
2
, inverters I
1
to I
4
, a NOR gate NR, PMOS and NMOS transistors P
1
and N
1
connected to each other in series, NMOS transistors N
2
and N
3
connected to each other in series between the lower and upper bank blocks
10
and
20
, and PMOS and NMOS transistors P
2
and N
4
connected to each other in series. The fuse F
1
is connected to the inverter I
1
, while the other fuse F
2
is connected to the inverter I
3
. The outputs of the inverters I
3
and I
2
are applied to the gates of the PMOS and NMOS transistors P
1
and N
1
, respectively, while the outputs of the inverters I
1
and I
4
are applied to the PMOS and NMOS transistors P
2
and N
4
, respectively. An output of the NOR gate NR is input commonly to the gates of the NMOS transistors N
2
and N
3
.
As shown, the selection circuit of the apparatus
30
is provided for only the MSB (most significant bit) BKADDR
4
of bank addresses. No such circuit is provided for other bits BKADDR
0
~BKADDR
3
, so that these bits BKADDR
0
~BKADDR
3
input to the apparatus
30
are automatically transmitted and applied to the lower and upper blocks
10
and
20
through lines L.
The operation of the bank selecting apparatus
30
in
FIG. 1
is as follows.
If thirty-two banks arranged in the lower and upper bank blocks
10
and
20
are in a normal operational state, the fuses F
1
and F
2
will not be cut. In this case, the PMOS transistors P
1
and P
2
and NMOS transistors N
1
and N
4
are turned off and the NOR gate NR outputs a high level signal which turns on the NMOS transistors N
2
and N
3
. As a result, all the bank address bits BKADDR
0
to BKADDR
4
input to the apparatus
30
are transmitted and applied to the lower and upper bank blocks
10
and
20
, so as to select banks out of all 32 banks.
If the fuse F
1
is cut by a failure of some banks in the upper bank block
20
, the NOR gate NR outputs a low level signal and turns off the NMOS transistors N
2
and N
3
. As a result, the bank address bit BKADDR
4
input to the apparatus is not transmitted to the lower and upper bank blocks
10
and
20
. However, the bank selecting apparatus
30
still allows the selection of the lower bank block
10
over the upper bank block
20
by the operation of the transistors P
1
, P
2
, N
1
and N
4
. For instance, a high level signal is applied to the gates of the PMOS and NMOS transistors P
1
and N
1
so that a logic value ‘0’ for the bit BKADDR
4
is established and applied to the upper bank block
20
. At the same time, a low level signal is applied to the gates of the PMOS and NMOS transistors P
2
and N
4
so that a logic value ‘1’ for the bit BKADDR
4
is established and applied to the lower bank block
10
. That is, different logic values for the bit BKADDR
4
are applied to the upper and lower bank blocks
20
and
10
. In this matter, only the lower bank block
10
becomes available for selection.
Meanwhile, if the other fuse F
2
is blown due to a failure of some banks in the lower bank block
10
, in accordance with the above-mentioned operational procedures, a logic value ‘1’ and a logic value ‘0’ for the same address bit BKADDR
4
are established by the transistors P
1
, P
2
, N
1
and N
4
and applied to the upper and lower bank blocks
20
and
10
, respectively, whereby only the upper bank block
20
becomes available for selection.
If degraded banks are present in either the lower bank block
10
or the upper bank block
20
, sixteen banks out of the thirty-two banks become available for use to provide a half-chip product, i.e., a 64M product which is a half-chip of a 128M product. If the banks
10
and
20
constitute a 1,144M product having 32 banks, then a 72M product having 16 banks will result in case of some failure in one of the blocks
10
and
20
.
However, conventional bank selecting apparatus such as the apparatus
30
implements a half-chip product only when degraded banks are included in either the upper or lower bank block. Namely, conventional techniques do not allow a repair of a memory chip if degraded banks are included in both upper and lower bank blocks. If few blocks in both the upper and lower blocks fail, then the entire memory chip having
32
banks becomes useless. This reduces throughput of memory devices which increases costs associated with fabricating and operating chip products.
SUMMARY OF THE INVENTION
Accordingly, the present invention is directed to an apparatus and method for selecting banks in a semiconductor memory device that substantially obviates one or more problems due to limitations and disadvantages of the related art.
An object of the present invention is to provide an apparatus and method for selecting banks in a semiconductor memory device that increases throughput of the semiconductor memory device and reduces the product cost by realizing a half-chip.
Another object of the present invention is to provide an apparatus and method for selecting banks in a semiconductor memory device that realizes a half-chip even if degraded banks are included in both upper and lower bank blocks.
A further object of the present invention is to provide an apparatus and method for selecting banks in a semiconductor memory device that realizes a half-chip by adjusting all bits including the most significant bit (MSB) of bank addresses to select operational banks.
Additional advantages, objects, and features of the invention will be set forth in part in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from practice of the invention. The objectives and other advantages of the invention may be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
To achieve these objects and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, in a semiconductor memory including an upper bank block and a lower bank block which are constructed with a plurality of banks selected by a plurality of bank addresses, respectively, an apparatus for selecting banks in a semiconductor memory includes a plurality of fuses cut selectively in accordance with locations of degraded banks included in the upper and lower bank blocks, a logic

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