Apparatus for scannable D-flip-flop which scans test data indepe

Details Apparatus for scannable D-flip-flop which scans test data indepe Apparatus for scannable D-flip-flop which scans test data indepe

1996-07-26

1997-11-18

Beausoliel, Jr., Robert W.

Excavating

371 225, 307418, G01R 3128

Patent

active

056895178

ABSTRACT:
The present invention discloses an apparatus for controlling and observing test data stored in scannable-D-flip-flops independent of a system clock, thereby making the scannable-D-flip-flops well suited for partial scanning Design-For-Test (DFT) techniques. Under the present invention, the scannable-D-flip-flop is comprised of two master latches and one slave latch such that the scannable-D-flip-flops may operate in a normal mode of operation or a scan/test mode of operation. During normal mode of operation, the first master latch operates together with the slave latch in response to the system clock. During the scan/test mode of operation, the second master latch operates together with the slave latch in response to a scan clock. Since the scanning of external test data is controlled by the scan clock, the conventional non-scannable D-flip-flops in the design, which are controlled by the system clock, maintain their previous states during a scanning operation. Also disclosed is a method for performance testing integrated circuits utilizing the scanning application of the scannable-D-flip-flops. This is accomplished by constructing a test circuit that spans the entire silicon die area. By using a special AC-TEST-MODE control signal, the scannable D-flip-flops are set to a "flow-through" mode to provide a direct path through the scannable flip-flops such that the test circuit forms an oscillator in which the frequency of the device can be measured.

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-E.B. Eichelberger et al., "A Logic Design Structure for LSI Testability," Reprinted from The Proceedings of the 14th Design Automation Conference by the Institute of Electrical and Electronics Engineers,Inc., pp. 206-212 (1977).

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