Apparatus for scan testing CMOS integrated systems

Details Apparatus for scan testing CMOS integrated systems Apparatus for scan testing CMOS integrated systems

1986-08-22

1988-11-01

Eisenzopf, Reinhard J.

Electricity: measuring and testing

Plural, automatically sequential tests

324158R, 324 73AT, 377 70, G01R 1512, G11C 1128

Patent

active

047822830

ABSTRACT:
Apparatus is disclosed for establishing scan-ring testing circuitry and control logic therefor on CMOS integrated circuit chips which can then be tested thereby during fabrication, after wire bonding and packaging, and while assembled and connected with other components on a printed circuit board. Tri-state buffers fabricated on the IC chip within the scan-ring control circuitry facilitate the operation of the scan-ring testing circuitry in several distinct operating modes which enable the functional circuitry of the integrated circuit to be electrically isolated from the associated signal pads for testing of the functional circuitry independently of circuitry connected to the signal pads, and for testing circuitry connected to the signal pads independently of the function circuitry of the chip.

REFERENCES:
patent: 4357703 (1982-11-01), Van Brunt
patent: 4495628 (1985-01-01), Zasio
patent: 4495629 (1985-01-01), Zasio et al.
patent: 4587480 (1986-05-01), Zasio
patent: 4621363 (1986-11-01), Blum

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