Apparatus for reducing the size of an arithmetic and logic unit

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G06F 752

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053175310

ABSTRACT:
In a circuit for accomplishing arithmetic operations and including an ALU; a first register for holding a dividend to be divided and intermediate and final results of the operation; a second register for holding a divisor; and apparatus for sequentially causing the dividend to be shifted left by one bit and the divisor subtracted from or added to the highest order bits of the dividend and partial remainders to provide a result which determines a quotient bit and thereby practice the operation of non-restore division, the improvement including: apparatus for performing an XNOR operation on the result of any carryout from any addition or subtraction operation and the value of the highest order bit of the dividend or the partial remainder; and apparatus for providing the result of the XNOR operation as the quotient bit to the arithmetic and logic unit.

REFERENCES:
patent: 4381550 (1983-04-01), Baker
patent: 4785393 (1988-11-01), Chu et al.
patent: 4891780 (1990-01-01), Miyoshi
patent: 5016210 (1991-05-01), Sprague et al.
J. J. F. Cavanagh, "Digital Computer Arithmetic Design and Implementation", pp. 236-259, 1984.
S. Sanyal, "An Algorithm for Non restoring Division", 1977, pp. 124-127.

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