Apparatus for reducing the instruction execution time in a compu

Details Apparatus for reducing the instruction execution time in a compu Apparatus for reducing the instruction execution time in a compu

1980-09-02

1982-10-12

Shaw, Gareth D.

Boots, shoes, and leggings

G06F 930

Patent

active

043542310

ABSTRACT:
Instructions which are read from a program memory of a control computer employing indirect addressing of a data memory are stored temporarily and sequentially in a buffer memory to form an execution queue. The absolute address to the data memory is generated by an address calculator by means of a base address derived from a reference memory in correspondence to an input address and by means of at least one address parameter which has been recorded in a register memory in connection with the execution of an instruction read from the buffer memory and transferred to a parameter register prior to the address calculation. In addition to each instruction, information is recorded in the buffer memory to indicate on the one hand whether the instruction is of the type which performs a write or read operation in the data memory and on the other hand whether it is of the type which enters address parameters in the register memory. This additional information is continually monitored and, when it shows that the address parameters will not be changed by any instruction in the queue ahead of a write or read instruction which has just entered the queue, the required address calculation process is initiated.

REFERENCES:
patent: 3490005 (1970-01-01), Anderson et al.
patent: 3644900 (1972-02-01), Mizoguchi
patent: 3766527 (1973-10-01), Briley
patent: 3916385 (1975-10-01), Parmar et al.
patent: 3949379 (1976-04-01), Ball
patent: 4042911 (1977-08-01), Bourke et al.
Computer, vol. 7, No. 11, Nov. 1974, pp. 24-38.
IBM Technical Disclosure Bulletin, vol. 10, No. 2, Jul. 1967.

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