Apparatus for reducing test data storage requirements for high s

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G01R 3128

Patent

active

046960058

ABSTRACT:
Apparatus for applying for a plurality of test cycles data specifying a plurality of test conditions to a multiple pin electronic circuit. A random access memory includes at a plurality of higher order addresses a complete data field for a plurality of test cycles. Some of said data fields include an operational code indicating that a minority of data bits in a field are to change in a consecutive number of following test cycles. A hold register is connected to receive each addressed row of test data from the memory. The higher order addresses of a memory addressed to produce complete data fields in the hold register. An operational code will be decoded to indicate a number of subsequent consecutive test cycles where a minority of data in the hold register are to be changed. The lower order addresses of the memory are subsequently addressed for a number of consecutive test cycles indicated by the operational code. The data contained in the lower order memory addresses is inserted in the hold register without changing the contents of a majority of hold register data bits.

REFERENCES:
patent: 3873818 (1975-03-01), Barnard
patent: 4070565 (1978-01-01), Borrelli
patent: 4291404 (1981-09-01), Steiner
patent: 4418388 (1983-11-01), Allgor et al.
patent: 4433414 (1984-02-01), Carey
patent: 4598245 (1986-07-01), Groves et al.

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