Electricity: measuring and testing – Fault detecting in electric circuits and of electric components – Of individual circuit component or element
Reexamination Certificate
2001-10-30
2002-09-24
Le, N. (Department: 2858)
Electricity: measuring and testing
Fault detecting in electric circuits and of electric components
Of individual circuit component or element
C324S1540PB, C307S043000
Reexamination Certificate
active
06456103
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates in general to systems for testing integrated circuits and in particular to an apparatus for reducing power supply noise in an integrated circuit under test resulting from state transitions of the logic it implements.
2. Description of Related Art
An integrated circuit (IC) tester can concurrently test a set of ICs in the form of die on a silicon wafer.
FIG. 1
is a block diagram illustrating a typical IC tester
10
connected through a probe card
12
to a set of similar IC devices under test (DUTs)
14
. Tester
10
uses pogo pins
15
or other means to connect various input and output terminals to a set of contacts
16
on probe card
12
. Probe card
12
includes a set of probes
18
for contacting input/output (I/O) pads
19
on the surface of each DUT
14
and provides conductive paths
20
linking contacts
16
to probes
18
. The paths through probe card
12
allow tester
10
to transmit test signals to DUT
14
and to monitor output signals produced by the DUT. Digital integrated circuits often include synchronous logic gates clocked in response to pulses of a periodic master clock signal (CLOCK). Therefore probe card
12
also provides a path
22
through which tester
10
may supply a CLOCK signal to each DUT
14
. The test system also includes a power supply
24
for supplying power to DUTs
14
as they are being tested. Probe card
12
connects power supply
24
to a power input pad
26
of each DUT
14
through probes
18
.
Each switching transistor within a DUT
14
has an inherent input capacitance, and in order to turn on or off the transistor, the transistor's driver must either charge or discharge the transistor's input capacitance. When a driver charges a transistor's input capacitance it draws charging current from power supply
24
. Once the transistor's input capacitance is fully charged, its driver need only supply a relatively small amount of leakage current needed to keep the transistor's input capacitance charged so that the transistor remains turned on or off. In DUTs implementing synchronous logic, most transistor switching occurs immediately after an edge of each CLOCK signal pulse. Thus immediately after each pulse of the CLOCK signal, there is a temporary increase in the power supply current I
1
input to each DUT
14
to provide the charging current necessary to change the switching states of various transistors within the DUT. Later in the CLOCK signal cycle, after those transistors have changed state, the demand for power supply current I
1
falls to a “quiescent” steady state level and remains there until the beginning of the next CLOCK signal cycle.
The signal paths
28
through which probe card
12
connects power supply
24
to each DUT
14
have an inherent impedance represented in
FIG. 1
by a resistance R
1
. Since there is a voltage drop between the output of power supply
24
and the power input
26
of DUT
14
, the supply voltage input VB to DUT
14
is somewhat less than the output voltage VA of power supply
24
, and although VA may be well-regulated, VB varies with the magnitude of current I
1
. After the start of each CLOCK signal cycle, the temporary increase in I
1
needed to charge switching transistor input capacitance increases the voltage drop across R
1
, thereby temporarily reducing VB. Since the dip in supply voltage VB occurring after each CLOCK signal pulse edge is a form of noise that can adversely affect the performance of DUTs
14
, it is desirable to limit its magnitude and duration. We can limit that noise by reducing the reactance of the paths
28
between power supply
24
and DUTs
14
, for example by increasing conductor size or by minimizing the length of path
28
. However there are practical limits to the amount by which we can reduce that reactance.
We can also reduce power supply noise by placing a capacitor C
1
on probe card
12
near the power supply input
26
of each DUT
14
.
FIG. 2
illustrates the behavior of supply voltage VD and current I
1
at the power input
26
of IC
14
in response to a pulse of the CLOCK signal input to IC
14
when capacitor C
1
is insufficiently large. Note that the temporary rise in I
1
above its quiescent level IQ following an edge of the CLOCK signal at time T
1
produces a temporary increase in voltage drop across R
1
that in turn produces a temporary dip in supply voltage VC below its quiescent level VQ.
FIG. 3
illustrates the behavior of VB and I
1
when capacitor C
1
is sufficiently large. Between CLOCK signal pulses, when DUT
14
is quiescent, capacitor C
1
charges to the quiescent level VQ of VP. Following a rising (or falling) edge of the CLOCK signal at time T
1
, when a DUT
14
temporarily demands more current, capacitor C
1
supplies some its stored charge to DUT
14
thereby reducing the amount of additional current power supply
24
must provide to meet the increased demand. As may be seen in
FIG. 3
, the presence of C
1
reduces the magnitude of the temporary voltage drop across R
1
and therefore reduces the magnitude of the dip in the supply voltage VB input to the DUT
14
.
For capacitor C
1
to adequately limit variation in VB, the capacitor must be large enough to supply the needed charge to DUT
14
and must be positioned close to DUT
14
so that the path impedance between C
1
and DUT
14
is very low. Unfortunately it is not always convenient or possible to mount a large capacitor on a probe card
12
near the power supply input terminal
26
of each DUT
14
.
FIG. 4
is a simplified plan view of a typical probe card
12
. IC tester
10
resides above the probe card and the wafer containing DUTs
14
is held below the probe card; Since the I/O terminals of IC tester
10
of
FIG. 1
are distributed over a relatively large area compared to the surface area of the wafer being tested, probe card
12
provides a relatively large upper surface
25
for holding the contacts
16
the tester accesses. On the other hand, the probes
18
(not shown) on the underside of probe card
12
that contact DUTs
14
on the wafer are concentrated under a relatively small central area
27
of probe card
12
.
The path impedance between contacts
16
on the upper surface
25
of card
12
and the probes
18
under area
27
is a function of the distance between each contact
16
and its corresponding probe. To minimize the distance between capacitors C
1
and the DUTS, the capacitors should be mounted on probe card
12
near (or above) the small central area
27
. However when a wafer includes a large number of ICs to be tested or an IC having a large number of densely packed terminals, there is not enough space to mount the required number of capacitors C
1
of sufficient size sufficiently close to central area
27
.
What is needed is a system for limiting the switching noise in power supply voltage at the power input terminals of the DUTs that does not require mounting large capacitors on the probe card close to the probes accessing the power input terminals.
SUMMARY OF THE INVENTION
During a test of an integrated circuit device under test (DUT) employing synchronous logic, the DUT experiences a temporarily increase in its demand for power supply current after each pulse of a clock signal input to the DUT because each clock signal pulse initiates state transitions of clocked logic devices within the DUT. The DUT needs the extra current to charge input capacitance of transistors forming those logic devices. It is an object of the invention to provide a means for limiting variation in power supply voltage at the power input terminal of a DUT arising from the transient increase in power supply current following each clock signal pulse, thus reducing the power supply noise at the DUT.
In accordance with one aspect of the invention, a charging current is supplied to the DUT's power input terminal from an auxiliary power supply source after each clock signal pulse to supplement a current continuously supplied by a main power supply during the
Eldridge Benjamin N.
Miller Charles A.
Bedell Daniel J.
Formfactor, Inc.
Le N.
Nguyen Vincent Q.
Smith-Hill and Bedell
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