Apparatus for reducing DC offset in a receiver

Details Apparatus for reducing DC offset in a receiver Apparatus for reducing DC offset in a receiver

2007-05-01

2007-05-01

Ha, Dac V. (Department: 2611)

Pulse or digital communications

Receivers

Automatic baseline or threshold adjustment

C375S328000, C375S344000, C375S345000, C455S182200, C455S192200, C455S214000, C455S234100, C455S240100

Reexamination Certificate

active

10343540

ABSTRACT:
Apparatus for reducing DC offset in a signal path of a conversion system comprising a front end circuit for providing an input signal having an a DC offset; an amplifier system coupled to the front end circuit to receive and amplify the input signal; a multi-bit sigma delta modulator for receiving the input signal from the amplifier system and providing a first bit quantizer; a DC adapt circuit coupled to the sigma delta modulator for receiving the first bit quantizer from the sigma delta modulator and for providing an operation to reduce DC offset; a digital to analog converter (DAC) coupled to the digital DC adapt circuit to provide an analog signal representative of the DC offset correction to the input of the amplifier system, wherein the digital DC adapt circuit and the DAC form a feedback path originating at the first bit of the multi bit sigma delta modulator to the input of the amplifier system.

REFERENCES:
patent: 6327313 (2001-12-01), Traylor et al.
patent: 6606359 (2003-08-01), Nag et al.
patent: 6996383 (2006-02-01), Hughes et al.
patent: 0709970 (1996-05-01), None
patent: 0474615 (1998-03-01), None
patent: 2328353 (1999-02-01), None

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