Apparatus for reducing computer system power consumption

Details Apparatus for reducing computer system power consumption Apparatus for reducing computer system power consumption

1995-06-07

1997-04-29

Davis, George B.

Boots, shoes, and leggings

395557, 364DIG1, 364DIG2, 364707, 364492, 365226, 365227, G06F 1500, G06F 1130

Patent

active

056258267

ABSTRACT:
A battery powered computer system determines when the system is not in use by monitoring various events associated with the operation of the system. The system preferably monitors the number of cache read misses and write operations, i.e., the cache hit rate, and reduces the system clock frequency when the cache hit rate rises above a certain level. When the cache hit rate is above a certain level, then it can be assumed that the processor is executing a tight loop, such as when the processor is waiting for a key to be pressed and then the frequency can be reduced without affecting system performance. Alternatively, the apparatus monitors the occurrence of memory page misses, I/O write cycles or other events to determine the level of activity of the computer system.

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Intel Corp. 386 SL Microprocessor Superset, System Design Guide, Chapter 14 "System and Power Management," pp. 14-1 to 14-23, 1990.
Intel Corp. 386 SL Microprocessor Superset, Programmers Reference Manual, Chapter 6 "System and Power Management," pp. 6-1 to 6-50; 10-4 to 10-7, 1990.

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