Coded data generation or conversion – Analog to or from digital conversion – Analog to digital conversion
Reexamination Certificate
2001-07-23
2003-05-06
Jeanpierre, Peguy (Department: 2819)
Coded data generation or conversion
Analog to or from digital conversion
Analog to digital conversion
C341S156000
Reexamination Certificate
active
06559787
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
The present invention is generally directed to a comparator for use in an analog-to-digital converter (ADC) and, more specifically, to an apparatus for reducing charge kickback in a dynamic comparator.
BACKGROUND OF THE INVENTION
Many low-power, high-speed application make use of a pipelined analog-to-digital (A/D) converter (or ADC). Pipelined ADCs provide high data throughput rates, occupy a comparatively small area of an integrated circuit, consume relatively little power, and minimize circuit complexity. Many of these advantages stem from the pipelined arrangement of multiple small A/D conversion stages.
All of the stages work concurrently. The first stage converts the most recent analog sample to a small number of digital bits (e.g., 2 bits) and passes an analog residue signal on to a subsequent stage. Each of the subsequent stages converts the analog residue signal from a preceding stage to digital bits and passes its own analog residue signal to the next stage.
Each stage comprises a dynamic comparator that latches the analog residue signal of a preceding stage and compares it to a reference level voltage. When the LATCH control signal for the dynamic comparator is disabled, the common source node of the input metal-oxide silicon field effect transistors (MOSFETs) of the dynamic comparator is not biased. During this time, the input MOSFETs do not have a channel formed and hence have no channel charge. When the LATCH control signal is enabled, the common source node of the input MOSFETs is biased and current is forced through the sources of the input devices, thereby creating a channel. This action pulls channel charge into the gates. The driving amplifier connected to the dynamic comparator inputs must instantaneously supply this channel charge. This phenomenon is called kickback charge injection by those skilled in the art of ADC design. Depending on the type of input device used in the comparator, the output of the amplifier either has charge injected into it or charge extracted from it. This causes the amplifier output to either fall below or rise above the correct output voltage.
After some time, the amplifier output recovers and the output voltage stabilizes to the correct value. Unfortunately, by this time, the comparator has already made its decision. Therefore, the drop or rise induced by the comparator kickback is seen by the comparator circuit as an offset in the compare threshold.
Therefore, there is a need in the art for analog-to-digital converters that are not susceptible to the effects of kickback charge. More particularly, there is a need for a dynamic comparator that can sample an analog signal line while causing minimal charge kickback to an amplifier driving the signal line.
SUMMARY OF THE INVENTION
To address the above-discussed deficiencies of the prior art, it is a primary object of the present invention to provide, in an advantageous embodiment of the present invention, a comparator comprising: 1) a first comparison circuit capable of receiving an input signal, wherein the first comparison circuit is enabled and compares the signal when a received LATCH signal is enabled and is disabled when the received LATCH signal is disabled; and 2) a second comparison circuit coupled to the input signal in parallel with the first comparison circuit, wherein an input stage of the second comparison circuit is substantially identical to an input stage of the first comparison circuit and the second comparison circuit is enabled and compares the input signal when the received LATCH signal is disabled and is disabled when the received LATCH signal is enabled.
In one embodiment of the present invention, an input capacitance of the input stage of the second comparison circuit is substantially identical to an input capacitance of the input stage of the first comparison circuit.
In another embodiment of the present invention, the input stage of the second comparison circuit is a single-ended differential pair input stage substantially identical to a single ended differential pair input stage of the first comparison circuit.
In yet another embodiment of the present invention, an input capacitance of the single-ended differential pair input stage of the second comparison circuit is substantially identical to an input capacitance of the single-ended differential pair input stage of the first comparison circuit.
It is another primary object of the present invention to provide, for use in an analog-to-digital (ADC) converter, an ADC stage capable of receiving a differential analog input signal, quantizing the differential analog input signal to a plurality of digital bits, and generating an output residue signal corresponding to a quantization error of the differential analog input signal. According to an exemplary embodiment of the present invention, the ADC stage comprises: 1) a first comparator coupled to the differential analog input signal, wherein the first comparator is enabled and compares the differential analog input signal when a received LATCH signal is enabled and is disabled when the received LATCH signal is disabled; and 2) a second comparator coupled to the differential analog input signal in parallel with the first comparator. An input stage of the second comparator is substantially identical to an input stage of the first comparator and the second comparator is enabled and compares the differential analog input signal when the received LATCH signal is disabled and is disabled when the received LATCH signal is enabled.
According to one embodiment of the present invention, an input capacitance of the input stage of the second comparator is substantially identical to an input capacitance of the input stage of the first comparator.
According to another embodiment of the present invention, the input stage of the second comparator is a differential pair input stage substantially identical to a differential pair input stage of the first comparator.
According to still another embodiment of the present invention, an input capacitance of the differential pair input stage of the second comparator is substantially identical to an input capacitance of the differential pair input stage of the first comparator.
The foregoing has outlined rather broadly the features and technical advantages of the present invention so that those skilled in the art may better understand the detailed description of the invention that follows. Additional features and advantages of the invention will be described hereinafter that form the subject of the claims of the invention. Those skilled in the art should appreciate that they may readily use the conception and the specific embodiment disclosed as a basis for modifying or designing other structures for carrying out the same purposes of the present invention. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the invention in its broadest form.
Before undertaking the DETAILED DESCRIPTION OF THE INVENTION below, it may be advantageous to set forth definitions of certain words and phrases used throughout this patent document: the terms “include” and “comprise,” as well as derivatives thereof, mean inclusion without limitation; the term “or,” is inclusive, meaning and/or; the phrases “associated with” and “associated therewith,” as well as derivatives thereof, may mean to include, be included within, interconnect with, contain, be contained within, connect to or with, couple to or with, be communicable with, cooperate with, interleave, juxtapose, be proximate to, be bound to or with, have, have a property of, or the like; and the term “controller” means any device, system or part thereof that controls at least one operation, such a device may be implemented in hardware, firmware or software, or some combination of at least two of the same. It should be noted that the functionality associated with any particular controller may be centralized or distributed, whether locally or remotely. Definitions for certain words and phrases are provided
Aude Arlo J.
Lewicki Laurence D.
Mohan Jitendra
Davis Munck, P.C.
Jeanpierre Peguy
Lauture Joseph
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