Coded data generation or conversion – Converter compensation
Reexamination Certificate
2001-10-05
2003-12-16
JeanPierre, Peguy (Department: 2819)
Coded data generation or conversion
Converter compensation
C341S144000, C341S136000
Reexamination Certificate
active
06664906
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to digital-to-analog converters (DAC) and more particularly to reducing the glitch energy at DAC outputs.
2. Background
Glitch energy is one measure of the output signal quality of a DAC. Glitch energy represents the difference in the amount of energy delivered to the output during a step in output level as compared to an ideal output step. Non-ideal DAC output transitions can result in signal distortions such as the output initially moving in a direction opposite that of the desired step, overshooting the step, or ringing after the step. The effect of these non-ideal transitions depends on the application of the DAC. In DACs used for driving graphics and video display devices, excessive glitch energy can cause color shifts at the borders of objects causing sparkles on the display screen.
DACs of the type commonly used for driving video and graphics display devices are called current mode DACs. Current mode DACs are made up of many current sources (e.g., 255 in an 8-bit linearly weighted DAC), each current source representing one or more least significant bits (LSB) of the DAC output. The currents are steered to either the output or to another node, typically ground, depending on the digital input code presented to the DAC for conversion. As shown in
FIG. 1
, the currents are summed and then converted to an output voltage by a resistor (R
LOAD
) connected from the output pad to ground.
The digital input code presented to the DAC typically controls the amount of current routed to the output in two ways. First, binarily weighted, and second linearly weighted. In a binary system, each bit of the digital input code controls an amount of current that corresponds to the significance of that bit in the digital input code. That is, bit 0 (the LSB) of the digital input code, switches 2
0
, i.e., one unit of current, bit 1 switches 2
1
, i.e., 2 units of current, and bit n switches 2
n
units of current. These units of current are often referred to as an LSB of current because the smallest unit of current is that controlled by the LSB of the digital input code. This type of system requires N switches for an N-bit code, which is the fewest possible in this type of design. However, it is difficult to make all the sources and switches sufficiently matched that good DAC linearity is maintained for code transitions between (2
M
−1) and (2
M
) for large M.
A least significant bit defines the smallest current source and switch size. As the amount of current is increased in the binary section of the DAC, the size of the transistors (or the number of elements in parallel) is increased proportionately.
In a linear system, data input codes, specifying non-zero currents, are decoded so as to enable one or more equal valued current sources. As the code increases, a new unit of current is added to the total (see Table 1 below). If the N system is entirely linear, each unit of current is an LSB and therefore 2
N
−1 switches are required for an N-bit digital input code (no switch for digital input code 0). Because all switches are substantially identical, linearity is easier to achieve than in a fully binarily weighted DAC. Unfortunately, a fully linearly weighted DAC requires a large amount of chip area and is therefore relatively expensive to implement.
To convert a digital input code to the control signals needed to drive the large number of current switches required by a linearly weighted DAC, a translation, referred to as a thermometer code is used. A thermometer decoder refers to an information processing network that takes an N bit input and produces a 2
N
bit output as shown in Table 1 below.
TABLE 1
Four-bit Thermometer code example
Binary Input
Current Switch (1 = to OUT, 0 = to Gnd)
Data
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
0000
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0001
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0010
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0011
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0100
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0101
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
.
.
.
1101
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
1110
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1111
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Many DAC designs use a combination of both binary and linear switch control. The DAC digital input code is “segmented” between binary and linear switch control. Binary is used for the least significant segment and linear for the most significant segment. Binary switch control is area efficient but tends to generate non-ideal output transitions because of the difficulty of balancing currents in differently sized switches. Linear switch control consumes more chip area but introduces fewer non-idealities into the output signal. The segmented DAC architecture provides a tradeoff between chip area and output signal quality. Examples of segmentation of an 8-bit DAC are given in Table 2 below.
TABLE 2
DAC segmentation examples
Linear Switch
Total
Segment-
Binary Switch
Linear
Weight
Switches
ation
Weights (LSBs)
Switches
(LSBs)
Required
2-6
1, 2
63
4
65
3-5
1, 2, 4
31
8
34
4-4
1, 2, 4, 8
15
16
19
5-3
1, 2, 4, 8, 16
7
32
12
The ideal transition of a DAC output when the input switches from code to code is a simple step with some reasonable rise time shorter than the smallest code duration. The actual transition may be significantly different. The difference from ideal in the energy transferred is the glitch energy.
The largest source of glitches is the timing skew between turning off one set of current switches while turning on a different set. This is usually due to the hazard in a binary encoding, for instance switching from code 00001111 to code 00010000. The code can briefly go to 00000000 or 00011111 causing overshoot or undershoot. Other causes of glitches are charge sharing in the switch (explained below) and capacitive feedthrough in the current switch from the switch driver. FIG.
2
(
a
) shows an ideal step and FIG.
2
(
b
) shows an example of a non-ideal transition.
FIG. 3
shows a block diagram of a conventional 8-bit DAC. This example uses 4—4 segmentation, i.e., 4 bits that are binarily decoded and 4 bits that are linearly decoded. The lower 4 bits and the decoded upper 4 bits are clocked into flip-flops to synchronize the output transitions between the bits. The flip-flops are connected to the switch drivers that control the current switches. The outputs of the current switches are summed and sent to the output pad.
FIG. 4
shows a conventional current switch control circuit along with other DAC circuit elements. The data input comes from the lower bits or from a thermometer decoder for the most significant bits. The data is clocked into a D-type flip-flop (DFF)
402
to synchronize the data to the clock. DFF
402
drives the current switch control signal generator that controls a pair of current steering transistors, PFET
410
and PFET
412
. PFET
414
is the current source whose current magnitude is set by the bias signal I
SET
and the size of PFET
414
. If the data clocked into DFF
402
is a zero, node
420
is low and node
422
is high. In this case PFET
412
is in a conducting state and PFET
410
is in a non-conducting state. All current is shunted to ground and no current (except current due to leakage or subthreshold conduction pathways) reaches the output pad from this current source of the DAC. Conversely, if DATA is high at the clock, then node
420
goes high, node
422
goes low, PFET
412
is turned off, and PFET
410
conducts the current to OUT. As shown in
FIG. 4
, the switch control signal generator outputs are applied respectively to node
420
and node
422
. Ideally, the current switch control signal generator output signals, as applied to nodes
420
,
422
, should cross at a voltage such that as one of the current switch transistors turns off, the other turns on at a complementary rate so that the total current through both transistors remains constant. In an ideal switch, the voltage on a node
416
between the current source and current switches would not chan
Blakely , Sokoloff, Taylor & Zafman LLP
Jean-Pierre Peguy
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