Excavating
Patent
1982-06-30
1985-03-05
Smith, Jerry
Excavating
364200, G06F 1100
Patent
active
045035350
ABSTRACT:
A number of intelligent nodes (bus interface units-BIUs and memory control units-MCUs) are provided in a matrix composed of processor buses (105) with corresponding error-reporting and control lines (106); and memory buses (107) with corresponding error-reporting and control lines (108). Error-detection mechanisms deal with information flow occuring across area boundaries. Each node (100, 101, 102, 103) has means for logging errors and reporting errors on the error report lines (106, 108). If an error recurs the node at which the error exists initiates an error message which is received and repropagated on the error report lines by all nodes. The error message identifies the type of error and the node ID at which the error was detected. Confinement area isolation logic in a node isolates a faulty confinement area of which the node is a part, upon the condition that the node ID in an error report message identifies the node as a node which is a part of a faulty confinement area. Logic in the node reconfigures at least part of the system upon the condition that the node ID in the error report message identifies the node as a node which is part of a confinement area which should be recofigured to recover from the error reported in the error report message.
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patent: 4191996 (1980-03-01), Chesley et al.
patent: 4347563 (1982-08-01), Poredes et al.
patent: 4371754 (1983-02-01), De et al.
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patent: 4438494 (1984-03-01), Budde et al.
Budde David L.
Carson David G.
Cornish Anthony L.
Johnson David B.
Peterson Craig B.
Fleming Michael R.
Intel Corporation
Lamb Owen L.
Smith Jerry
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