Multiplex communications – Data flow congestion prevention or control
Reexamination Certificate
2008-03-25
2008-03-25
Rao, Seema S. (Department: 2616)
Multiplex communications
Data flow congestion prevention or control
C370S230100
Reexamination Certificate
active
10613347
ABSTRACT:
A traffic management processor for processing different types of traffic flows includes a departure time calculator (DTC) circuit for calculating a departure time for each packet received, a content addressable memory (CAM) device coupled to the DTC circuit and having a plurality of rows, each row including a first portion for storing the departure time for a corresponding packet and including a second portion for storing a bit indicating a traffic type for the packet, and compare logic coupled to the CAM device and configured to determine which of the departure times stored in the CAM device is the earliest.
REFERENCES:
patent: 5875173 (1999-02-01), Ohgane et al.
Advanced Traffic Management for Multiservice ATM Networks, www.net.com, Pub. Dec. 15, 2001, 22 pgs.
Agere Ads Additional PaloadPlus Processor to Product Line, Agere Press Release, Nov. 29, 2000, 3 pgs.
Architecture and Design of Function Specific Wire-Speed Routers for Optical Internetworking, publishing by Entridia Corp., Dec. 6, 2000, 60 pgs.
ATLAS I: A General-Purpose, Single-Chip ATM Switch with Credit-Based Flow Control, IEEE Hot Interconnects IV Symposium Proceedings, Standford, CA, Pub. Aug. 15-17, 1996, 11 pgs.
CSIX-L1:Common Switch Interface Specification-L1, published by CSIX, Aug. 5, 2000 , 72 pgs.
Efficient Fair Queuing Using Deficit Round Robin, M Shreedhar, George Varghese, Pub. Data Unknown, 12 pgs.
genFlow CAN-2500gF OC48c Multiprotocol Traffic Management Coprocessor, Acorn Networks, Pub. Date Unknown, 4 pgs.
genFlow OC-48c Multiprotocol Traffic Management Coprocessor, Acorn Networks, Pub. Date unknown, 4 pgs.
Hierarchial Packet Fair Queueing Algorithms, Jon C.R. Bennett, Hui Zhang, Pub. Date Unknown, 14 pgs.
iFlow Networking using Smart Memory Technology, Silicon Access Networks, Pub. Oct. 2000, 10 pgs.
Implementation of ATLASI: a Single-Chip ATM Switch with Backpressure, IEEE Hot Interconnects IV Symposium Proceedings, Standford, CA, Pub. Aug. 13-15, 1998, 12 pgs.
Introduction to ATM Traffic Management, www.net.com, Pub. Dec. 15, 2000, 15 pgs.
Network Processing New Concepts Using Smart Memory Technology, Silicon Access Networks, Publ. Oct. 2000, 7 pgs.
Orologic's Traffi-Shaping Chip Set Handles ATM, IP, TechWeb.com, Nov. 30, 2000, 2 pgs.
PaceMaker 2.4 (formerly QoSCore, Orologic Press Release, Nov. 30, 2000 1 page.
PaceMaker 2.4 OC-48 Traffic Management Engine, Vitesse Semiconductor Corp., Pub 2000, 2 pgs.
PayloadPlus Routing Switch Processor, Lucent Technologies, Apr. 2000, 6 pgs.
PMC-Sierra's ATM Chip Set Provides the Traffic Management and Switch Fabric Core for Ericsson's AXD 301 ATM Switch, PMC-Sierra, Publ. Dec. 12, 2000, 10 Pgs.
Scalable Harware Earliest-Deadline-First Scheduler for ATM Switching Networks, 18th IEEE Reeal-Time Systems Symposium, Pub. 1997, 9 pgs.
Simulation Sutdy of Statistical Delays in an ATM Switch Using EDF Scheduling, Dept. of Computer Science, North Carolina State University, Pub. Jun. 24, 1999, 25 pgs.
Smart Memory Technology in the MAN, Silicon Access Networks, Pub. Oct. 2000, 6 pgs.
Smart Memory Technology Target Markets, Silicon Access Networks, Pub. Oct. 2000, 5 pgs.
Start-time Queuing: A Scheduling Algorithm for Integrated Services Packet Switching Networks, Pawan Goyal, Harrick M. Vin and Haichen Cheng, Distributed Multimedia Computing Laboratory, Dept. Computer Sciences, University of Texas at Austin, Pub. 1996, 12.
Statistical Delay Bounds Oriented Packet Scheduling Algorithms in High Speed Networks, by Kai Zhu, North Carolina State University, Pub. 2000, 6 pgs.
Traffic Scheduling in Packet-Switched Networks: Analysis, Design and Implementation, university of California, Santa Cruz, Pub. Jun. 1996, 107 pgs.
Traffic Stream Processor MXT 4400, Conexant, Pub. Data Unknown, 5 pgs.
Vitesse Announces Industry's First OC-48c Traffic Management Engine, Vitesse Semiconductor Corp., Sep. 28, 2000, 2 pgs.
Vitessee Announces Industry's First OC-48c Traffic Management Engine, Orologic Press Release, Nov. 30, 2000 2 pgs.
Wan Fast Intelligent Router, Silicon Access Netowrks, Pub. Oct. 23, 2000 4 pgs.
WF2Q: Worst-case Fair Weighted Fair Queueing, Jon C.R. Bennett, Hui Zhang, Pub. Date Unknown, 9 pgs.
What is a Network Processor?, Vitesse Semiconductor Corp., Pub Data Unknown, 4 pgs.
Wire Speed Quality of Service Over Ethernet, Switchcore, Pub. May 8, 2000, 19 pgs.
ZettaCom Delivers In-Service System Scalability with Highly Integrated OC-192 Hybrid Switch Fabric, biz.yahoo.com, Pub Nov. 11, 2000, 2 pgs.
Zettacom: Hurry Up and Wait, www.lightreading.com, Pub. Nov. 29, 2000, 2 pgs.
Khanna Sandeep
Srinivasan Varadarajan
NetLogic Microsystems, Inc.
Paradice III William L
Rao Seema S.
Wu Jianye
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