Patent
1995-11-27
1996-09-03
Swann, Tod R.
395284, G06F 1202
Patent
active
055532705
ABSTRACT:
A computer system includes a processor having a primary cache, and a secondary cache data store, cache tag store, and memory controlled by a memory controller. The cache tag store, secondary cache data store, and memory share a common address bus. The secondary cache data store and the memory share a common data bus. In addition, some of the bits of the address bus are saved and fed directly to the memory. The memory controller provides for pipelined secondary cache accesses, during which a corresponding tag from the cache tag store is compared in the processor against the required memory address to determine if the data is located in the secondary cache. If the data is not in the secondary cache, the memory controller asserts the appropriate signals to obtain the data from memory. Because some of the address bits are fed directly to the memory, the setup time for memory control signals can be satisfied during the comparison of the cache data tag. In addition, while the memory reference is being performed, the original version of the address bits may be updated to perform page mode addressing of the secondary cache.
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Digital Equipment Corporation
Fisher Arthur W.
Maloney Denis G.
McGuinness Lindsay G.
O'Neill David J.
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