Apparatus for providing digitally-adjustable floating MOS capaci

Miscellaneous active electrical nonlinear devices – circuits – and – Specific identifiable device – circuit – or system – Utilizing a three or more electrode solid-state device

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327365, 327524, 327554, 327403, H01L 2708

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active

057149070

ABSTRACT:
A method and an apparatus for providing an adjustable floating capacitance between a first node and a second node in an integrated circuit. First and second transistors having commonly coupled gates are coupled between the input and output nodes of a digitally-adjustable floating MOS capacitor. The source and drain of the first transistor are coupled to the input node, while the source and drain of the second transistor are coupled to the output node. A switch responsive to an enable signal is coupled to the gates of the first and second transistors. In response to the enable signal, the switch alternatively couples the gates of the first and second transistors to either a first potential or a second potential. When the gates of the first and second transistors are coupled to the first potential, a first capacitance is realized between the input and output nodes. When the gates of the first and second transistors are coupled to the second potential, a second capacitance is realized between the first and second nodes.

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"A Novel CMOS Digital Clock and Data Decoder", Mel Bazes & Roni Ashuri, IEEE Journal of Solid-State Circuits, vol. 27, No. 12, Dec. 1992, pp. 1934-1940.

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