Apparatus for providing block erasing in a flash EPROM

Static information storage and retrieval – Floating gate – Particular biasing

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Details

365218, 36523003, 3652385, G11C 1134, G11C 700, G11C 800

Patent

active

050653644

ABSTRACT:
A flash EPROM memory array having vertical blocking is described. The array is organized into a plurality of vertical (column) blocks. Each block includes a source region switch which couples all the source regions in the memory cells in its respective block to a programming potential, ground or a disturb inhibit potential. Each of the blocks may be erased without disturbing the programming in the other blocks.

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