Apparatus for programming non-volatile memory with reduced...

Details Apparatus for programming non-volatile memory with reduced... Apparatus for programming non-volatile memory with reduced...

2008-04-08

2008-04-08

Nguyen, Tuan T. (Department: 2824)

Static information storage and retrieval

Floating gate

Particular connection

C365S185270, C365S185110

Reexamination Certificate

active

07355888

ABSTRACT:
Non-volatile storage elements are programmed in a manner that reduces program disturb by using modified pass voltages. In particular, during the programming of a selected storage element associated with a selected word line, a higher pass voltage is applied to word lines associated with previously programmed non-volatile storage elements in the set than to word lines associated with unprogrammed and/or partly programmed non-volatile storage elements in the set. The pass voltage is sufficiently high to balance the channel potentials on the source and drain sides of the selected word line and/or to reduce leakage of charge between the boosted channel regions. Optionally, an isolation region is formed between the boosted channel regions by applying a reduced voltage on one or more word lines between the selected word line and the word lines that receive the higher pass voltage.

REFERENCES:
patent: 5043940 (1991-08-01), Harari
patent: 5172338 (1992-12-01), Mehrotra et al.
patent: 5386422 (1995-01-01), Endoh
patent: 5522580 (1996-06-01), Varner, Jr.
patent: 5570315 (1996-10-01), Tanaka
patent: 5621684 (1997-04-01), Jung
patent: 5677873 (1997-10-01), Choi et al.
patent: 5715194 (1998-02-01), Hu
patent: 5774397 (1998-06-01), Endoh et al.
patent: 5818757 (1998-10-01), So et al.
patent: 5887145 (1999-03-01), Harari et al.
patent: 5973962 (1999-10-01), Kwon
patent: 5991202 (1999-11-01), Derhacobian et al.
patent: 6011287 (2000-01-01), Itoh et al.
patent: 6046935 (2000-04-01), Takeuchi et al.
patent: 6049494 (2000-04-01), Sakui et al.
patent: 6061270 (2000-05-01), Choi
patent: 6107658 (2000-08-01), Itoh et al.
patent: 6181599 (2001-01-01), Gongwer
patent: 6222762 (2001-04-01), Guterman
patent: 6456528 (2002-09-01), Chen
patent: 6522580 (2003-02-01), Chen et al.
patent: 6525964 (2003-02-01), Tanaka et al.
patent: 6614688 (2003-09-01), Yeom et al.
patent: 6859395 (2005-02-01), Matsunaga et al.
patent: 6859397 (2005-02-01), Lutze et al.
patent: 6987694 (2006-01-01), Lee
patent: 7046568 (2006-05-01), Cernea
patent: 7061807 (2006-06-01), Tanaka et al.
patent: 7099193 (2006-08-01), Futatsuyama
patent: 7161833 (2007-01-01), Hemink
patent: 7184309 (2007-02-01), Matsunaga et al.
patent: 7196928 (2007-03-01), Chen
patent: 2002/0110019 (2002-08-01), Satoh et al.
patent: 2002/0126532 (2002-09-01), Matsunaga et al.
patent: 2003/0147278 (2003-08-01), Tanaka et al.
patent: 2004/0057287 (2004-03-01), Cernea
patent: 2004/0105308 (2004-06-01), Matsunaga
patent: 2004/0109357 (2004-06-01), Cernea
patent: 2004/0255090 (2004-12-01), Guterman
patent: 2005/0024939 (2005-02-01), Chen
patent: 2005/0174852 (2005-08-01), Hemink
patent: 2005/0226055 (2005-10-01), Guteman
patent: 2006/0126390 (2006-06-01), Gorobets
patent: 2006/0140007 (2006-06-01), Cernea
patent: 2006/0158947 (2006-07-01), Chan
patent: 2007/0047314 (2007-03-01), Goda et al.
patent: 2007/0171719 (2007-07-01), Hemink
S. Aritome et al., “Reliability Issues of Flash Memory Cells,” Proceedings of the IEEE, New York, vol. 81, No. 5, May 1, 1993, pp. 776-788.
Jung, et al., “A 3.3V 128Mb Multi-Level NAND Flash Memory for Mass Storage Applications,” ISSCC96, Session 2, Flash Memory, Paper TP 2.1, IEEE, pp. 32-33, slide supplement pp. 20-21, 346-347 (1996).
Jung, et al., “A 117-mm2 3.3-V Only 128-Mb Multilevel NAND Flash Memory for Mass Storage Applications,” IEEE Journal of Solid-State Circuits, vol. 31, No. 11, Nov. 1996, pp. 1575-1583.
A. Modelli et al., “Basic feasibility constraints for multilevel CHE-programmed flashmemories,” IEE Trans. on Electron Devices, vol. 48, No. 9, Sep. 2001, pp. 2032-2042.
T. Nozaki, et al., “A 1-Mb EEPROM with MONOS Memory Cell for Semiconductor Disk Application,” IEEE Journal of Solid-State Circuits, vol. 26, No. 4 Apr. 1991, pp. 497-501.
K.D. Suh, et al., “A 3.3V 32 Mb NAND Flash Memory with Incremental Step Pulse Programming Scheme,” Journal of Solid-State Circuits, vol. 30, No. 11, Nov. 1995, pp. 1149-1155.
Office Action dated Mar. 23, 2007 in U.S. Appl. No. 11/313,023.

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