Computer graphics processing and selective visual display system – Computer graphics processing – Graphic manipulation
Reexamination Certificate
2000-02-17
2003-10-21
Luu, Matthew (Department: 2672)
Computer graphics processing and selective visual display system
Computer graphics processing
Graphic manipulation
C345S629000, C345S634000
Reexamination Certificate
active
06636233
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to an apparatus and a method of synthesizing a background and a graphic in translucence to thereby two-dimensionally display resultant image.
2. Description of the Related Art
When an object is seen through a colored glass or sea, the object is seen as if the object has a color of the glass or sea. It is called translucent-processing to make images of an object to be obtained when the object is seen through translucent medium such as a colored glass.
FIG. 1
illustrates an image obtained by carrying out translucent-processing. Though the illustrated image is a two-dimensional one, the image is displayed in three-dimensional axes for the sake of explanation.
The image consists of background images SC
1
, SC
2
and SC
3
and graphic images SP
1
, SP
2
and SP
3
. Herein, the graphic images SC
1
, SC
2
and SP
1
have a color to be translucent-processed. The background and graphic images SC
3
, SP
3
, SC
2
, SP
2
, SP
1
and SC
1
are overlapped one another in this order from a bottom to a top, to thereby form the image.
FIG. 2
is a block diagram of a conventional two-dimensional graphic engine.
The illustrated two-dimensional graphic engine is comprised of a central processing unit (CPU)
1
, a two-dimensional (2D) graphics processor
2
, a character ROM
3
, and a display device
4
.
The 2D graphics processor
2
includes a CPU interface
5
, a ROM interface
6
, a background painter
7
, a graphic painter
8
, a color synthesizer
9
, and a controller
10
. The above-mentioned background images SC
1
, SC
2
and SC
3
are made by the background painter
7
, and the graphic images SC
1
, SC
2
and SP
1
are made by the graphic painter
8
.
The character ROM
3
stores data about images to be displayed in the display device
4
. The stored data is mapped in the character ROM
3
in such a manner as illustrated in FIG.
10
.
As mentioned below, since the color synthesizer
9
includes a pallet RAM
20
, a pallet code, that is, an address for the pallet RAM
20
, is stored in the character ROM
3
pixel by pixel. Signals S
3
indicative of address data of the character ROM
3
are transmitted between the character ROM
3
and the ROM interface
6
.
The display device
4
is comprised of a cathode ray tube (CRT) or a liquid crystal display (LCD),for instance, and displays images thereon. The display device
4
receives signals S
4
indicative of RGB data from the color synthesizer
9
, and also receives synchronization signals S
17
such as V
SYNC
and H
SYNC
, from the controller
10
.
The CPU interface
5
receives signals S
2
from CPU
1
, indicating where a graphic is to be displayed on a display screen of the display device
4
, and specification of the 2D graphic engine.
The ROM interface
6
adjusts a timing at which the 2D graphics processor
2
provides an address to the character ROM
3
to thereby gain data from the character ROM
3
.
The background painter
7
processes backgrounds, that is, adheres data stored in the character ROM
3
, entirely on a screen of the display device
4
. The background painter
7
receives signals S
5
from the CPU interface
5
, indicating that which data among data stored in the character ROM
3
is to be displayed on a screen of the display device
4
.
The graphic painter
8
makes a graphic of 16×16 dot, for instance, in the character ROM
3
, and transmits a signal S
7
to the CPU interface
5
, indicating that on which coordinate system the thus made graphic is to be displayed in the display device
4
. A coordinate system which the graphic painter
8
recognizes has to be greater than a display screen of the display device
4
. If a coordinate system which does not exist in the display screen is indicated, a designated graphic cannot be displayed.
The signal S
2
transmitted between CPU
1
and the CPU interface
5
, the signal S
3
transmitted between the character ROM
3
and the ROM interface
6
, the signal S
4
transmitted between the display device
4
and the color synthesizer
9
, the signal S
5
transmitted between the CPU interface
5
and the background painter
7
, the signal S
6
transmitted between the CPU interface
5
and the color synthesizer
9
, and the signal S
7
transmitted between the CPU interface
5
and the graphic painter
8
are all interactive signals, because CPU
1
monitors operation of the parts, and varies parameters in the parts.
The controller
10
transmits signals S
12
to S
17
to the display device
4
, the CPU interface
5
, the ROM interface
6
, the background painter
7
, the graphic painter
8
, and the color synthesizer
9
so that the parts
4
to
9
can properly work.
FIG. 3
is a block diagram illustrating a structure of the graphic painter
8
. The graphic painter
8
is comprised of a selector
11
, a parameter RAM
12
, a graphic ROM address calculator
13
, a graphic analyzer
14
, a graphic buffer
15
, an output device
16
, and a timing producer
17
.
The selector
11
selects one of an address signal ZB transmitted from the timing producer
17
and an EX-ADD signal provided from an external circuit (not illustrated), indicative of a predetermined value, and transmits the selected one to the parameter RAM
12
as an address.
The parameter RAM
12
stores such data as illustrated in FIG.
11
. The parameter RAM
12
includes address word lines by the number equal to the number of graphics which can be stored in the graphic painter
8
. Each of addresses indicates a number of graphics. Parameters as illustrated in
FIG. 11
are designed to be assigned to each of graphics. When a graphic is displayed, CPU
1
determines the parameters, and then, displays the graphic accordingly.
On receipt of an address, the parameter RAM
12
transmits parameters P
1
to P
5
which are indicative of an address, a coordinate on X-axis, a coordinate on Y-axis, the number of graphics, and a translucence signal, respectively. The parameter RAM
12
receives a data signal EX-DATA and a write enable signal EX-WE from an external circuit (not illustrated).
The graphic ROM address calculator
13
calculates an address for the character ROM
3
to be displayed, based on the parameter P
1
, and transmits the thus calculated address to the character ROM
3
as R-ADD.
The graphic analyzer
14
receives the parameters P
2
and P
3
from the parameter RAM
12
, and judges whether a graphic associated with a given address number is within a displayable area. The graphic analyzer
14
transmits both a signal ZK
1
indicative of a number of graphics to be displayed, and a FIFO write enable signal F-WE to the graphic buffer
15
.
The graphic buffer
15
stores background graphics therein.
The output device
16
receives image data R-DATA from the character ROM
3
, and establishes a timing at which next data is transmitted to the color synthesizer
9
, based on the parameters P
2
, P
3
, P
4
and P
5
. The output device
16
transmits a signal S
11
including a data signal H-DATA for a display buffer, a write enable signal H-WE for a display buffer, and an address signal H-ADD for a display buffer.
The timing producer
17
receives both a main clock signal Si and a signal S
13
by which the graphic painter
8
is controlled, and transmits a graphic number signal ZB to the selector
11
, a graphic number enable signal ZBDEN to the graphic analyzer
14
, and a graphic buffer request signal Z-RQ to the graphic buffer
15
. In addition, the timing producer
17
receives both a signal EMP indicating that the graphic buffer is empty and a graphic number signal ZKO from the graphic buffer
15
, and transmits an output request signal S-RQ to the output device
16
.
FIG. 4
is a block diagram of the color synthesizer
9
. As illustrated in
FIG. 4
, the color synthesizer
9
is comprised of a color synthesis controller
50
, first and second graphic selectors
51
and
52
, first and second display buffers
53
and
54
, selectors
55
and
56
, an output controller
57
, a translucence processor
58
, a selector
59
, and a pallet RAM
60
Luu Matthew
McGinn & Gibb PLLC
NEC Electronics Corporation
LandOfFree
Apparatus for processing two-dimensional images and method... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Apparatus for processing two-dimensional images and method..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Apparatus for processing two-dimensional images and method... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3145710