Apparatus for processing signalling messages in an asynchronous

Details Apparatus for processing signalling messages in an asynchronous Apparatus for processing signalling messages in an asynchronous

1990-03-29

1992-03-31

Olms, Douglas W.

Multiplex communications

Wide area network

Packet switching

3701101, 395800, 364DIG1, H04L 100, H04L 522, H04L 2530

Patent

active

051014033

ABSTRACT:
The apparatus comprises a protocol processor circuit connected to a network, a memory having a transmit memory and a receive memory, a transmit control memory and a receive control memory. The memories are connected to the processor circuit via a data bus and to a level 2.2 processor by a bus. The control memories are of the FIFO type, with the transmit control memory being written to by the high level 2.2 processor and being read from by the processor circuit, and with the receive control memory being written to by the processor circuit and read from by the level 2.2 processor. The processor circuit transmits and receives cells containing signalling information, and it performs level 2.1 function of the protocol: detecting transmission errors on a cell-by-cell basis, detecting loss for added cells, splitting up a message delivered by the level 2.2 processor into cells, and de-interlacing cells relating to a plurality of messages on reception.

REFERENCES:
IEEE/IEICE Global Telecommunications Conference 1987, Conference Record, Tokyo, Nov. 15-18, 1987, vol. 3, pp. 2095-2099, IEEE, New York, U.S.; T. Ae et al., "A design of high speed network controller".
IEEE Network, vol. 3, No. 1, Jan. 1989, pp. 17-22, IEEE, New York, U.S.; M. J. Rider: "Protocols for ATM access networks".

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