Apparatus for processing interrupts in microprocessing systems

Details Apparatus for processing interrupts in microprocessing systems Apparatus for processing interrupts in microprocessing systems

1976-01-29

1977-07-05

Chapnick, Melvin B.

Boots, shoes, and leggings

G06F 304, G06F 918

Patent

active

040343499

ABSTRACT:
Circuitry external of a microprocessor determines priority between different peripheral devices requesting interrupts to generate a restart vector and a signal granting priority to one of the interrupt-requesting devices. The peripheral device loads its status and address into two addressable registers connected to a common system bus. The restart vector is loaded into the instruction register of the microprocessor. The microprocessor treats the restart vector as an instruction to store the contents of the program counter in memory and loads certain bits of the restart vector into the program counter. These bits represent the starting address of a subroutine of eight instructions for analyzing the interrupt. An interrupt is recognized and the status and identification of the interrupting device is stored in a single instruction cycle. On the next instruction cycle the first instruction of the interrupt analysis routine may begin. During this analysis routine the contents of the two addressable registers may be read out to determine which device caused the interrupt and what action should be taken in view of the status of the interrupting device. Provision is made for processing interrupts other than those requested by peripheral devices, and each type of interrupt generates a different restart vector thus selecting a different address as the first instruction address of the interrupt analysis routine.

REFERENCES:
patent: 3061192 (1962-10-01), Terzian
patent: 3560935 (1971-02-01), Beers
patent: 3710324 (1973-01-01), Cohen et al.
patent: 3800287 (1974-03-01), Albright
patent: 3828325 (1974-08-01), Stafford et al.
patent: 3909790 (1975-09-01), Shapiro et al.
patent: 3924240 (1975-12-01), Given

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