Multiplex communications – Pathfinding or routing – Switching a message which includes an address header
Reexamination Certificate
2000-01-31
2003-12-09
Chin, Wellington (Department: 2664)
Multiplex communications
Pathfinding or routing
Switching a message which includes an address header
C370S395530, C370S429000
Reexamination Certificate
active
06661792
ABSTRACT:
This application claims the benefit of Korean patent application No. 3309/1999, filed Feb. 1, 1999, which is hereby incorporated by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an Ethernet switch system, and more particularly, to an apparatus for processing a data packet of a layer 2 Ethernet switch system, and a method thereof.
2. Description of the Background Art
FIG. 1
is a schematic view of a layer 2 Ethernet switch system in accordance with a conventional art.
As shown in the drawing, the conventional layer 2 Ethernet switch system includes a media access control (termed as MAC, hereinafter)
11
connected to an ethernet network
10
through a physical layer (not shown) and detecting a packet from an inputted bit stream; a search engine
12
for searching MAC addresses stored in a search memory
13
and determining an output port of the packet detected by the MAC
11
; a search memory
13
for storing overall MAC addresses of the Ethernet switch system; a packet memory
14
for temporarily storing the output packet of the search engine
12
; and a control unit
15
for controlling the operation of the whole system. A plurality of input/output FIFOs (first-in-first-out) buffers
4
a
,
4
b
,
5
a
,
5
b
,
6
a
and
6
b
are connected between the MAC
11
, the search engine
12
and the packet memory
14
, so as to buffer the packet.
In this respect, the Ethernet network
10
is connected to a plurality of devices (not shown) and implemented as a twisted pair cable, a coaxial cable and an optical fiber.
The operation of the layer 2 Ethernet switch system in accordance with the conventional art constructed as described above will now be explained with reference to the accompanying drawings.
FIG. 2
shows a frame structure of a data packet on an IEEE 802.3 standard. As shown in the drawing, each data packet includes a preamble, a start of frame delimiter (SFD) indicating a start of a data portion of a message, a destination address (DA) field, a source address (SA) field, a length/type field, a data field having a real packet data, and a frame check sequence (FCS) of error information.
When a bit stream including a data packet in the frame structure is inputted to a predetermined port of the Ethernet switch system through the Ethernet
10
, it is matched in the physical layer (not shown) and is inputted to the MAC layer.
As well as detecting the preamble and the SFD of the data packet, the MAC
11
sequentially detects the destination address (DA), the source address (SA), the length/type, the data and the frame check sequence (FCS), and then performs a cyclic redundancy checking (CRC) in the FCS, so as to check whether the inputted packet is valid or not.
Upon checking, if the packet is valid one, the MAC
11
outputs the detected packet to the first FIFO
4
a.
After the packet detecting operation by the MAC
11
is completed, that is, after the packet detected by the MAC
11
is outputted to the first FIFO
4
a
, the search engine
12
accesses the packet from the first FIFO
4
a
, and searches the search memory
13
according to a pre-defined search algorithm so as to determine an output port of the accessed packet.
That is, the search engine
12
reads the destination address (DA) and a source address (SA) of a header of the packet and checks whether or not the destination address as read is stored in the search memory
13
.
If the destination address is stored in the search memory
13
, the search engine
12
searches a port number corresponding to the destination address as read from the search memory
13
and determines an output port of the packet. And, as the output port of the MAC packet is determined, the search engine
12
outputs an ending signal to the control unit
15
and temporarily stores the packet in the packet memory
14
through the FIFO
5
a.
Upon receipt of the ending signal from the search engine
12
, the control unit
15
checks the state of the FIFOs
5
b
and
4
b
, or
5
b
and
6
b
and of the MAC
11
. In case that the FIFOs and the MAC
11
are not busy, the control unit
15
controls the FIFOs
5
b
and
4
b
, or
5
b
and
6
b
and of the MAC
11
so that the packet stored in the packet memory
14
is transferred to the Ethernet
10
.
On the other hand, if the destination address of the packet is not stored in the search memory
13
, the search engine
12
records an MAC address (a source address and a destination address) of the currently inputted packet in the search memory
13
and then stores a corresponding packet in the packet memory
14
.
Accordingly, the packet stored in the packet memory
14
is flooded under the control of the control unit
15
. That is, in case that the destination address of the packet is not recorded in the search memory
13
or in case that the destination address of the packet is all ‘1’ (broadcast address), the packet is transferred to all of the MAC ports other than the MAC port that currently received the packet.
The search engine
12
determines an output port by reading the destination address and the source address from the packet stored in the first FIFO
4
a
at the time point when the packet detected by the MAC
11
is stored in the first FIFO
4
a
. That is, the search engine
12
does not access the first FIFO
4
a
until all of the packets shown in
FIG. 2
are detected.
As a result, a transfer time of the packet received by the input port of the MAC to the output port of the MAC is lengthened, causing a problem in that the whole system is degraded in view of efficiency.
In addition, in case that a resource is additionally included so as to resolve the problem, its production cost is increased as much.
SUMMARY OF THE INVENTION
Therefore, an object of the present invention is to provide an apparatus for processing a data packet of an Ethernet switch system which is capable of improving an efficiency of the system by minimizing a delay time in transferring the packet from an input port to an output port, and a method thereof.
Another object of the present invention is to provide an apparatus for processing a data packet of an Ethernet switch system which can be implemented by a few resources and a small memory structure, and a method thereof.
To achieve these and other advantages and in accordance with the purposed of the present invention, as embodied and broadly described herein, there is provided an apparatus for processing a data packet of an Ethernet switch system in which packet information is transferred from a first device to a second device based on a field information of the packet inputted through an Ethernet, comprising at least one MAC for detecting the field information of the packet received from the first device through the Ethernet, and at least one search engine for determining an output port of the packet to be outputted to the second device based on a source address and a destination address provided from the MACs on a real-time basis before the MAC completes the detecting operation of the packet, wherein the search engine is directly connected to the MAC.
In order to obtain the above objects, there is also provided an apparatus for processing a data packet of an Ethernet switch system, comprising at least one MAC for detecting the packet from a bit stream, a search memory where MAC addresses are stored, at least one search engine positioned at the same layer with the MAC and determining an output port of the packet before the MAC completes the detecting operation of the packet based on an address detected and provided by the MAC on a real-time basis and the MAC address searched in the search memory, wherein the search engine is directly connected to the MAC, FIFOs for buffering the packet detected by the MAC, and a control unit for performing an overall control operation.
In order to obtain the above objects, there is also provided a method for processing a data packet of an Ethernet switch system in which packet information is transferred from a first device to a second device on the basis of field information of the pack
Chin Wellington
Ha Yvonne Q.
LG Information & Communications Ltd.
Morgan & Lewis & Bockius, LLP
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