Multiplex communications – Pathfinding or routing – Through a circuit switch
Reexamination Certificate
1999-08-25
2002-09-03
Yao, Kwang Bin (Department: 2664)
Multiplex communications
Pathfinding or routing
Through a circuit switch
Reexamination Certificate
active
06445699
ABSTRACT:
BACKGROUND OF THE INVENTION
Field of the Invention
The invention lies in the electronics and communications fields. Specifically, the invention relates to an apparatus for processing and generating data using a digital signal processor. The apparatus includes an interface unit allocated to a signal processor. The interface reads in and preprocesses the data to be processed and/or the data required for processing, and/or generates data and for the signal processor to pick up and/or picks up, postprocesses and outputs data which the signal processor processes or generates and supplies for pickup. The interface unit has a preprocessing and postprocessing device provided for pre- and postprocessing the data. A memory device is provided for supplying the data that have been preprocessed and are to be postprocessed for the signal processor or the preprocessing and postprocessing device to pick up. The preprocessing and postprocessing device has an expansion/compression device which can be used to expand the data read in and to compress the data to be output. The memory device is set up such that the preprocessing and postprocessing device and the signal processor can have quasi-simultaneous read and write access.
Such methods and apparatuses are used, by way of example but by no means exclusively, in ISDN private branch exchanges. ISDN private branch exchanges are systems, generally installed on a telecommunication subscriber's premises, which can be used to connect a multiplicity of telecommunications terminals (telephones, fax machines, modems and the like) which are connected to them to one another and/or to one or more subscriber lines (exchange lines) in a telecommunications network.
Patent Abstracts of Japan Vol. 095, No. 002, Mar. 31, 1995 & JP 06 326870 A discloses an apparatus, for example, which has a dual port RAM for processing data interchanged between a modem and a fax more efficiently. With that configuration it is possible for the modem and the fax to write to and read from the dual port RAM at the same time. The modem has a signal processor, which processes the data, and a front-end processor connected upstream of the signal processor for preprocessing the data.
A conventional design of an ISDN private branch exchange is illustrated in FIG.
4
. There, the private branch exchange includes one or more transceivers
11
a
,
11
b
, . . .
11
n
, a digital signal processor
12
and a control and switching device
13
; the transceivers
11
a
,
11
b
, . . .
11
n
and the digital signal processor
12
are connected to the control and switching device
13
via connection lines
14
.
The transceivers
11
a
,
11
b
, . . .
11
n
can have telecommunications terminals and/or one or more exchange lines connected to them. The number of transceivers
11
a
,
11
b
, . . .
11
n
to be provided is geared to the number and types of telecommunications terminals and exchange lines to be connected. In the exemplary embodiment under consideration, the transceiver
11
a
may be designed for connecting one or more conventional (analog) telecommunications terminals, the transceiver
11
b
may be designed for connecting one or more (digital) ISDN telecommunications terminals, and the transceiver
11
n
may be designed for connecting one or more ISDN exchange lines. In this context, the term “designed” is to be understood to mean constructed and configured.
Calls incoming via an exchange line from the telephone company are forwarded via the transceiver
11
n
to the control and switching device
13
and from there to the telecommunications terminal addressed by the call; outgoing calls from the telecommunications terminals are likewise routed to the control and switching device
13
and from there are connected to the specified location, which can be another of the telecommunications terminals connected to the private branch exchange or can be one of the connected exchange lines.
The control and switching device
13
supplies the signal processor
12
with all the data and information received by the private branch exchange from the telecommunications terminals and telephone company exchange lines. The signal processor
12
processes the received data as necessary to produce modified data, or generates new data and outputs or returns the data to the control and switching device
13
. The control and switching device
13
receives the data and outputs them to the addressed telecommunications terminals and exchange lines in place of the data received by the telecommunications terminals and exchange lines.
This means that, to name just a few from an almost arbitrary number of examples, it is possible, among other things, to:
generate specific signal tones (call connected signal, busy signal) and/or specific messages (for example a message indicating that the call will not be connected because a telecommunications terminal with the service indicator “telephone” is calling a telecommunications terminal with the service indicator “fax”) and the like;
feed back the subscriber's speech into the telephone muted on the telephone so that it can be overheard by the speaker; and
connect more than two subscribers and/or telecommunications terminals to one another (conference call connection).
However, experience shows that the tasks to be dealt with by the signal processor to achieve this take it to its performance limits very quickly. The result of this is that either a number of signal processors have to be used or certain convenience features of the private branch exchange have to be sacrificed. This is obviously a considerable disadvantage.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide an apparatus for processing and generating data with a digital signal processor, which overcomes the above-mentioned disadvantages of the heretofore-known devices and methods of this general type and which enables even work-intensive processing and generation of data using low-power and/or a minimal number of signal processors.
With the foregoing and other objects in view there is provided, in accordance with the invention, an apparatus for processing and generating data, comprising:
a digital signal processor;
an interface unit connected to the signal processor, the interface unit being adapted to read in and preprocess data for the signal processor and to postprocess and output data from the signal processor;
the interface unit including a preprocessing and post-processing device for preprocessing and postprocessing the data, and a memory device connected to the preprocessing and postprocessing device and to the signal processor;
the memory device being divided into four memory areas including two memory areas reserved for write access by the preprocessing and postprocessing device and for read access by the signal processor, and two memory areas reserved for write access by the signal processor and for read access by the preprocessing and postprocessing device.
The memory, therefore, allowing quasi-simultaneous read and write access by the preprocessing and postprocessing device and by the signal processor
In other words, an interface unit is provided which is allocated to the signal processor and reads in and preprocesses the data to be processed and/or data required for processing and/or generating data and supplies it for the signal processor to pick up and/or picks up, postprocesses and outputs data which the signal processor processes or generates and supplies for pickup. To this end, the interface unit has a pre- and postprocessing device provided for pre- and postprocessing the data, and a memory device provided for supplying the data which has been preprocessed and is to be postprocessed for the signal processor or the pre- and postprocessing device to pick up. The pre- and postprocessing device has an expansion/compression device which can be used to expand the data read in and to compress the data to be output. The memory device is designed such that the pre- and postprocessing device and the signal processor can have read and/or write access to it at virtuall
Greenberg Laurence A.
Harper Kevin C.
Locher Ralph E.
Siemens Aktiengesellschaft
Stemer Werner H.
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