Apparatus for predicting overlapped storage operands for move ch

Details Apparatus for predicting overlapped storage operands for move ch Apparatus for predicting overlapped storage operands for move ch

1992-07-28

1996-01-30

Lane, Jack A.

395375, G06F 934, G06F 1206

Patent

active

054887070

ABSTRACT:
An apparatus is presented and proved for detecting storage operand overlap for instructions having identical overlap detection requirements as the move character (MVC) instruction. The apparatus is applicable to all Enterprise Systems Architecture (ESA)/390 addressing modes encompassing access register addressing for either 24 bit or 31 bit addressing. S/370 addressing in 24 bit and 31 bit modes are also supported by the proposed apparatus and treated as special cases of access register addressing. In addition, the apparatus is extended to support other addressing modes with an example provided to include a 64 bit addressing mode. A fast parallel implementation of the apparatus is also presented. The apparatus results in a one cycle savings for all invocations of the MVC instruction which comprises approximately 2% of the dynamic instruction stream of a representative instruction mix. The one cycle savings results in a 21 percent improvement in the performance of the execution of the MVC instruction for the frequent case (84%) when the operand length is less than or equal to eight bytes and a 9 percent improvement in performance for the less frequent case (16%) in which the operand length is greater than eight bytes.

REFERENCES:
patent: 5278960 (1994-01-01), Shibuya
patent: 5297266 (1994-03-01), Tanaka

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