Chemistry: electrical and wave energy – Apparatus – Electrolytic
Reexamination Certificate
2001-05-10
2003-05-13
Nguyen, Nam (Department: 1741)
Chemistry: electrical and wave energy
Apparatus
Electrolytic
C204S229800, C204S230700, C204S297100, C204S297140
Reexamination Certificate
active
06562204
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Technical Field
This invention relates generally to electroplating methods and apparatus and, in particular, to processes and apparatus for potential-controlled electrodeposition of metal into small integrated circuit features such as vias and trenches.
2. Description of Related Art
Conductive interconnections on integrated circuits typically take the form of trenches and vias. In modern submicron integrated circuits, trenches and vias are typically formed by a “damascene” or “dual damascene” process as described, for example, in the reference
ULSI Technology
, Eds. C. Y. Chang and S. M. Sze (McGraw-Hill, 1996, pp. 444-445.) In damascene processing, an interlayer dielectric (typically SiO
2
) is deposited atop a planarized layer containing, for example, a metal via. The top dielectric layer is patterned and etched, typically using conventional photolithographic procedures. Metal is then deposited into features and on the flat field region atop the features, typically first by CVD, PVD and then by electrodeposition. The metal layer is typically planarized resulting in the desired metallic pattern. Dual damascene processing is similar but makes use of two patterning and etching steps and typically fills features with metal spanning more than one layer in a single metallization step. A more complete description of damascene and dual damascene processing is found in the cited reference.
As the art moves towards integrated circuits having reduced feature sizes, it becomes increasingly difficult to form electrically conductive metallizations such as vias, contacts and conductors. Techniques for forming such metallizations include physical vapor deposition (PVD), chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD) and electrochemical deposition (also referred to as electroplating or electrodeposition) of metals such as copper. Electroplating is particularly well suited for the formation of small embedded damascene feature metallization due to the ability to readily control the growth of the electroplated film for bottom-up filling without voids, and due to the superior electrical conductivity characteristics of the electroplated film. However, there are also several obstacles which need to be overcome to fully realize these advantages.
One challenge facing damascene and dual damascene processing techniques is the difficulty of initiating the growth of the metal film within recessed features without forming voids or seams. In typical PVD and some CVD processes, metal may preferentially deposit near the top of recessed features leading to a “bottleneck” shape. Further plating of metal onto the bottleneck may result in sealing the top of the feature before completely filling the feature with metal, creating a void. Voids increase the resistance of the conductor over its designed value due to the absence of planned-for conductor. Also, trapped electrolyte in sealed voids may corrode the metal. This may lead to degraded device performance or device failure in extreme cases.
The problem of electroplating metal into integrated circuit features without the formation of voids or seams is the subject of previously filed U.S. patent application Ser. No. 09/410,170, commonly assigned with the present invention, (hereinafter “prior application”), now abandoned and incorporated herein by reference. The prior application identified previously unrecognized problems with conventional electroplating techniques and described a four-step approach to overcome them or to mitigate their deleterious effects on the electroplating processes. The four phases relate to the following: 1) the entry of the wafer into the electroplating bath, including procedures to reduce or eliminate corrosion of thin metal seed layers already deposited on the surfaces of recessed features (“entry phase”); 2) the conformal growth of metal seed layers having sufficient thickness to support delivery of current to the bottom of the feature and permit subsequent bottom-up feature filling (“initiation phase”); 3) preferential deposition of metal onto the bottom of high aspect ratio (“AR”) features (having AR's greater than about 0.5) leading to bottom-up filling and the reduction of the ARs; and 4) rapid filling of low AR features in a rapid substantially conformal manner until the required metal thickness is achieved.
The methods described in the prior application relate generally to constant current (“galvanostatic”) or controlled current (“galvanodynamic”) processes. Thus, the current was the parameter controlled and the voltage was understood to take on whatever value necessary to achieve the specified current. Use of galvanostatic or galvanodynamic processes has the advantage of requiring typically simpler and less expensive power sources than those typically required in the practice of controlled-voltage (“potentiodynamic”) processes.
Prior art and literature pertaining to potentiostatic and potentiodynamic electroplating is limited in comparison with the literature and prior art related to galvanostatic and galvanodynamic electroplating. Controlled-potential electroplating is typically a more complicated process than controlled current electroplating for several reasons. 1) Controlled-current power supplies are more readily available at lower cost while only a limited number of (typically) more expensive power supplies are available for controlled-potential service. 2) A “four wire” system is typically required in controlled-potential electroplating in order to compensate adequately for potential drop in current-carrying wires and for contact resistances. For applications requiring excellent metal thickness uniformity, such as the integrated circuit fabrication processes described here, a reference electrode probe is advisable.
The present invention describes several advantages to be obtained with the use of controlled-potential electroplating processes for small recessed features in integrated circuit devices. Equipment filly to take advantage of potentiodynamic electroplating processes for the four-step filling of integrated circuit features with metal is also described.
SUMMARY OF THE INVENTION
Controlled-potential electroplating provides an effective method of electroplating metals onto the surfaces of high aspect ratio recessed features of integrated circuit devices. The rate of electroplating is strongly dependent on current density which is correlated with the applied voltage. Thus controlled-potential methods provide tighter control of the electroplating process than controlled-current methods. In addition, controlled-potential electroplating methods are more universally applicable, from wafer to wafer, essentially independent of the number, size, and distribution of recessed features on the wafer, than are controlled-current methods.
Controlling the potential during electroplating provides a process to mitigate corrosion of a metal seed layer on recessed features in a layer of an integrated circuit structure. The corrosion is due to contact of the seed layer with an electrolyte solution during the entry phase. The potential can also be controlled to provide conformal plating over the seed layer during the initiation phase and bottom-up filling of the recessed features during the third, bottom-up filling phase. At each phase, a constant cathodic voltage, pulsed cathodic voltage, or ramped cathodic voltage can be used.
An apparatus for controlled-potential electroplating includes a reference electrode placed near the surface to be plated and at least one cathode sense lead to measure the potential at points on the circumference of the integrated circuit structure.
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Contolini Robert
Mayer Steven T.
Reid Jonathan
Nicolas Wesley A.
Skjerven Morrill LLP
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