Patent
1995-06-05
1996-09-03
Bowler, Alyssa H.
395800, G06F 906
Patent
active
055532560
ABSTRACT:
Maximum throughput or "back-to-back" scheduling of dependent instructions in a pipelined processor is achieved by maximizing the efficiency in which the processor determines the availability of the source operands of a dependent instruction and provides those operands to an execution unit executing the dependent instruction. These two operations are implemented through a number of mechanisms. One mechanism for determining the availability of source operands, and hence the readiness of a dependent instruction for dispatch to an available execution unit, relies on the early setting of a source valid bit during allocation when a source operand is a retired or immediate value. This allows the ready logic of a reservation station to begin scheduling the instruction for dispatch.
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Fetterman Michael A.
Hinton Glenn J.
Martell Robert W.
Papworth David B.
Bowler Alyssa H.
Follansbee John
Intel Corporation
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