Active solid-state devices (e.g. – transistors – solid-state diode – Physical configuration of semiconductor – With peripheral feature due to separation of smaller...
Patent
1995-06-07
1997-01-14
Crane, Sara W.
Active solid-state devices (e.g., transistors, solid-state diode
Physical configuration of semiconductor
With peripheral feature due to separation of smaller...
257 48, 257734, 257536, 371 211, 371 225, G01R 3100, G01R 3128, H01L 2166
Patent
active
055942733
ABSTRACT:
Wafer level testing of a wafer (500) is accomplished by dividing the integrated circuits of the wafer into a plurality of segmented bus regions (514, 516, and 518 for example). Each bus region is formed having its own set of test conductors (520-530) wherein each set of test conductors are isolated from all other sets of test conductors on the wafer. Each test conductor has at least one contact pad (531-546) where each contact pad lies within a periphery of the integrated circuits' active areas. By forming pads over ICs and by sub-dividing the bus structure of test conductive lines, more high powered ICs can be tested in a wafer-level manner with fewer problems associated with speed, power, throughput, and routing problems. In addition, all contact pads are formed within the periphery of the ICs but no contact pads are formed over active circuitry so that yield is improved.
REFERENCES:
patent: 4281449 (1981-08-01), Ports et al.
patent: 4379259 (1983-04-01), Varadi et al.
patent: 4467400 (1984-08-01), Stopper
patent: 4472483 (1984-09-01), Shimamoto et al.
patent: 4489397 (1984-12-01), Lee
patent: 4518914 (1985-05-01), Okubo et al.
patent: 4519035 (1985-05-01), Chamberlain
patent: 4523144 (1985-06-01), Okubo et al.
patent: 4628991 (1986-12-01), Hsiao et al.
patent: 4783695 (1988-11-01), Eichelberger et al.
patent: 4849847 (1989-07-01), McIver et al.
patent: 4855253 (1989-08-01), Weber
patent: 4884122 (1989-11-01), Eichelberger et al.
patent: 4918811 (1990-04-01), Eichelberger et al.
patent: 4937203 (1990-06-01), Eichelberger et al.
patent: 4956602 (1990-09-01), Parrish
patent: 4961053 (1990-10-01), Krug
patent: 4967146 (1990-10-01), Morgan et al.
patent: 4968931 (1990-11-01), Littlebury et al.
patent: 5012187 (1991-04-01), Littlebury
patent: 5047711 (1991-09-01), Smith et al.
patent: 5059899 (1991-10-01), Farnworth et al.
patent: 5089772 (1992-02-01), Hatada et al.
patent: 5130644 (1992-07-01), Ott
patent: 5206181 (1993-04-01), Gross
patent: 5239191 (1993-08-01), Sakumoto et al.
patent: 5241266 (1993-08-01), Ahmad et al.
patent: 5279975 (1994-01-01), Devereaux et al.
patent: 5294776 (1994-03-01), Furuyama
patent: 5307010 (1994-04-01), Chiu
patent: 5389556 (1995-02-01), Rostoker et al.
patent: 5399505 (1995-03-01), Dasse et al.
Intel Corporation, Intel486.TM. DX Microprocessor Data Book, Jun. 1991, pp. 127-141, Order Number: 240440-004.
Dasse Edward C.
Day Lawrence J.
Kost Donald R.
Crane Sara W.
Motorola Inc.
Williams Alexander Oscar
Witek Keith E.
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