Apparatus for performing single error correction and double erro

Details Apparatus for performing single error correction and double erro Apparatus for performing single error correction and double erro

1978-10-16

1980-12-23

Atkinson, Charles E.

Excavating

371 38, G06F 1112, G11C 2900

Patent

active

042414466

ABSTRACT:
This relates to an apparatus for performing single error correction, double error detection of binary words, each section of the apparatus processing one byte of raw data. Each section includes first logic means for producing a first plurality of intermediate sector matrix parity outputs. A second logic means receives one of the first plurality of intermediate sector matrix parity outputs and a second plurality of intermediates matrix parity outputs from other sections and generates therefrom a syndrome signal. A third logic means receives this syndrome signal and syndrome signals from other sections and generates therefrom the corrected data bits.

REFERENCES:
patent: 3825893 (1974-07-01), Bossen et al.
patent: 3949208 (1976-04-01), Carter
patent: 3982226 (1976-09-01), Bunker et al.
patent: 4139148 (1979-02-01), Scheuneman et al.
Motorola Semiconductors Brochure, Modules MC8500P and MC8501P, Cyclic Redundancy Check Character Generator and Error Pattern Register, 1973.

Affiliated with

Also associated with

Rating

Apparatus for performing single error correction and double erro does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Apparatus for performing single error correction and double erro, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Apparatus for performing single error correction and double erro will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2246574