Apparatus for performing modulo arithmetic with three-port adder

Details Apparatus for performing modulo arithmetic with three-port adder Apparatus for performing modulo arithmetic with three-port adder

1991-03-06

1993-08-03

Nguyen, Long T.

Boots, shoes, and leggings

364768, G06F 738, G06F 750

Patent

active

052335534

ABSTRACT:
A method and apparatus for emulating the intermediate 16-bit truncation of the address in the 8086 architecture using a 32-bit adder. The preferred embodiment of the invention adds the displacement, base address, and segment base values in a three-port carry save adder. The displacement value and base address are also added together in a two-port full adder. The outputs of the three-port carry save adder and two-port full adder are then compared to determine whether a carry from bit 16, if any, resulted from the addition of the displacement and base address value or the addition of the segment base value. A logic unit determines whether a carry into bit position 16 of the linear address is modified. If the carry is the result of the addition of the segment base value to the effective address, the carry is not modified. If the carry is the result of the addition of the base and displacement value, the carry is modified by forcing the bit position 16 to zero.

REFERENCES:
patent: 4831570 (1989-05-01), Abiko
patent: 4852040 (1989-07-01), Oota
patent: 4893267 (1990-01-01), Alsup et al.

Affiliated with

Also associated with

Rating

Apparatus for performing modulo arithmetic with three-port adder does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Apparatus for performing modulo arithmetic with three-port adder, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Apparatus for performing modulo arithmetic with three-port adder will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2276960