Apparatus for performing floating point arithmetic operations an

Details Apparatus for performing floating point arithmetic operations an Apparatus for performing floating point arithmetic operations an

1986-03-12

1989-06-13

Harkcom, Gary V.

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G06F 738

Patent

active

048398462

ABSTRACT:
An operation unit capable of performing round processing at a high speed in a floating point operation. A circuit for detecting an overflow on the condition of a signal representing all 1's in an output of a mantissa shifter and a signal representing round-up, a carry look-ahead circuit and a circuit for generating a round precision signal are provided. When the overflow takes place, the mantissa is produced as "1". The operation unit is compatible to single, double and extended precisions recommended by Institute of Electrical and Electronic Engineers (IEEE).

REFERENCES:
patent: 4130879 (1978-12-01), Cushing
patent: 4338675 (1982-07-01), Palmer et al.
patent: 4442498 (1984-04-01), Rosen
patent: 4468748 (1984-08-01), Blaw et al.
patent: 4476523 (1984-10-01), Beauchamp
patent: 4484259 (1984-11-01), Palmer et al.
patent: 4562553 (1985-12-01), Mattedi et al.
patent: 4644490 (1987-02-01), Kobayashi
"A Proposed Standard for Binary Floating Point Arithmetic", IEEE Computer, Mar. 1981, pp. 51-62.
Twaddell, "Higher Performance Marks Floating Point Chips", Computer Designs, pp. 24-30, Apr. 15, 1986.

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